1 What: /sys/bus/cxl/flush 1 What: /sys/bus/cxl/flush
2 Date: Januarry, 2022 2 Date: Januarry, 2022
3 KernelVersion: v5.18 3 KernelVersion: v5.18
4 Contact: linux-cxl@vger.kernel.org 4 Contact: linux-cxl@vger.kernel.org
5 Description: 5 Description:
6 (WO) If userspace manually unb 6 (WO) If userspace manually unbinds a port the kernel schedules
7 all descendant memdevs for unb 7 all descendant memdevs for unbind. Writing '1' to this attribute
8 flushes that work. 8 flushes that work.
9 9
10 10
11 What: /sys/bus/cxl/devices/memX/firm 11 What: /sys/bus/cxl/devices/memX/firmware_version
12 Date: December, 2020 12 Date: December, 2020
13 KernelVersion: v5.12 13 KernelVersion: v5.12
14 Contact: linux-cxl@vger.kernel.org 14 Contact: linux-cxl@vger.kernel.org
15 Description: 15 Description:
16 (RO) "FW Revision" string as r 16 (RO) "FW Revision" string as reported by the Identify
17 Memory Device Output Payload i 17 Memory Device Output Payload in the CXL-2.0
18 specification. 18 specification.
19 19
20 20
21 What: /sys/bus/cxl/devices/memX/ram/ 21 What: /sys/bus/cxl/devices/memX/ram/size
22 Date: December, 2020 22 Date: December, 2020
23 KernelVersion: v5.12 23 KernelVersion: v5.12
24 Contact: linux-cxl@vger.kernel.org 24 Contact: linux-cxl@vger.kernel.org
25 Description: 25 Description:
26 (RO) "Volatile Only Capacity" 26 (RO) "Volatile Only Capacity" as bytes. Represents the
27 identically named field in the 27 identically named field in the Identify Memory Device Output
28 Payload in the CXL-2.0 specifi 28 Payload in the CXL-2.0 specification.
29 29
30 30
31 What: /sys/bus/cxl/devices/memX/ram/ <<
32 Date: May, 2023 <<
33 KernelVersion: v6.8 <<
34 Contact: linux-cxl@vger.kernel.org <<
35 Description: <<
36 (RO) For CXL host platforms th <<
37 this attribute conveys a comma <<
38 specific cookies that identifi <<
39 for the volatile partition of <<
40 class-ids can be compared agai <<
41 published for a root decoder. <<
42 that the endpoints map their l <<
43 matching platform class, misma <<
44 and there are platform specifi <<
45 side-effects that may result. <<
46 <<
47 <<
48 What: /sys/bus/cxl/devices/memX/pmem 31 What: /sys/bus/cxl/devices/memX/pmem/size
49 Date: December, 2020 32 Date: December, 2020
50 KernelVersion: v5.12 33 KernelVersion: v5.12
51 Contact: linux-cxl@vger.kernel.org 34 Contact: linux-cxl@vger.kernel.org
52 Description: 35 Description:
53 (RO) "Persistent Only Capacity 36 (RO) "Persistent Only Capacity" as bytes. Represents the
54 identically named field in the 37 identically named field in the Identify Memory Device Output
55 Payload in the CXL-2.0 specifi 38 Payload in the CXL-2.0 specification.
56 39
57 40
58 What: /sys/bus/cxl/devices/memX/pmem <<
59 Date: May, 2023 <<
60 KernelVersion: v6.8 <<
61 Contact: linux-cxl@vger.kernel.org <<
62 Description: <<
63 (RO) For CXL host platforms th <<
64 this attribute conveys a comma <<
65 specific cookies that identifi <<
66 for the persistent partition o <<
67 class-ids can be compared agai <<
68 published for a root decoder. <<
69 that the endpoints map their l <<
70 matching platform class, misma <<
71 and there are platform specifi <<
72 side-effects that may result. <<
73 <<
74 <<
75 What: /sys/bus/cxl/devices/memX/seri 41 What: /sys/bus/cxl/devices/memX/serial
76 Date: January, 2022 42 Date: January, 2022
77 KernelVersion: v5.18 43 KernelVersion: v5.18
78 Contact: linux-cxl@vger.kernel.org 44 Contact: linux-cxl@vger.kernel.org
79 Description: 45 Description:
80 (RO) 64-bit serial number per 46 (RO) 64-bit serial number per the PCIe Device Serial Number
81 capability. Mandatory for CXL 47 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
82 Memory Device PCIe Capabilitie 48 Memory Device PCIe Capabilities and Extended Capabilities.
83 49
84 50
85 What: /sys/bus/cxl/devices/memX/numa 51 What: /sys/bus/cxl/devices/memX/numa_node
86 Date: January, 2022 52 Date: January, 2022
87 KernelVersion: v5.18 53 KernelVersion: v5.18
88 Contact: linux-cxl@vger.kernel.org 54 Contact: linux-cxl@vger.kernel.org
89 Description: 55 Description:
90 (RO) If NUMA is enabled and th 56 (RO) If NUMA is enabled and the platform has affinitized the
91 host PCI device for this memor 57 host PCI device for this memory device, emit the CPU node
92 affinity for this device. 58 affinity for this device.
93 59
94 60
95 What: /sys/bus/cxl/devices/memX/secu <<
96 Date: June, 2023 <<
97 KernelVersion: v6.5 <<
98 Contact: linux-cxl@vger.kernel.org <<
99 Description: <<
100 (RO) Reading this file will di <<
101 that device. Such states can b <<
102 a sanitization is currently un <<
103 for persistent memory: 'locked <<
104 sysfs entry is select/poll cap <<
105 upon completion of a sanitize <<
106 <<
107 <<
108 What: /sys/bus/cxl/devices/memX/secu <<
109 Date: June, 2023 <<
110 KernelVersion: v6.5 <<
111 Contact: linux-cxl@vger.kernel.org <<
112 Description: <<
113 (WO) Write a boolean 'true' st <<
114 sanitize the device to securel <<
115 This is done by ensuring that <<
116 whether it resides in persiste <<
117 or the LSA, is made permanentl <<
118 is appropriate for the media t <<
119 the device to be disabled, tha <<
120 HPA ranges. This permits avoid <<
121 management, relying instead fo <<
122 transitions between software p <<
123 states. If this file is not pr <<
124 support for the operation. <<
125 <<
126 <<
127 What /sys/bus/cxl/devices/memX/secu <<
128 Date: June, 2023 <<
129 KernelVersion: v6.5 <<
130 Contact: linux-cxl@vger.kernel.org <<
131 Description: <<
132 (WO) Write a boolean 'true' st <<
133 secure erase user data by chan <<
134 all user data areas of the dev <<
135 the device to be disabled, tha <<
136 HPA ranges. This permits avoid <<
137 management, relying instead fo <<
138 transitions between software p <<
139 states. If this file is not pr <<
140 support for the operation. <<
141 <<
142 <<
143 What: /sys/bus/cxl/devices/memX/firm <<
144 Date: April, 2023 <<
145 KernelVersion: v6.5 <<
146 Contact: linux-cxl@vger.kernel.org <<
147 Description: <<
148 (RW) Firmware uploader mechani <<
149 this directory can be used to <<
150 firmware for CXL devices. The <<
151 documented in sysfs-class-firm <<
152 <<
153 <<
154 What: /sys/bus/cxl/devices/*/devtype 61 What: /sys/bus/cxl/devices/*/devtype
155 Date: June, 2021 62 Date: June, 2021
156 KernelVersion: v5.14 63 KernelVersion: v5.14
157 Contact: linux-cxl@vger.kernel.org 64 Contact: linux-cxl@vger.kernel.org
158 Description: 65 Description:
159 (RO) CXL device objects export 66 (RO) CXL device objects export the devtype attribute which
160 mirrors the same value communi 67 mirrors the same value communicated in the DEVTYPE environment
161 variable for uevents for devic 68 variable for uevents for devices on the "cxl" bus.
162 69
163 70
164 What: /sys/bus/cxl/devices/*/modalia 71 What: /sys/bus/cxl/devices/*/modalias
165 Date: December, 2021 72 Date: December, 2021
166 KernelVersion: v5.18 73 KernelVersion: v5.18
167 Contact: linux-cxl@vger.kernel.org 74 Contact: linux-cxl@vger.kernel.org
168 Description: 75 Description:
169 (RO) CXL device objects export 76 (RO) CXL device objects export the modalias attribute which
170 mirrors the same value communi 77 mirrors the same value communicated in the MODALIAS environment
171 variable for uevents for devic 78 variable for uevents for devices on the "cxl" bus.
172 79
173 80
174 What: /sys/bus/cxl/devices/portX/upo 81 What: /sys/bus/cxl/devices/portX/uport
175 Date: June, 2021 82 Date: June, 2021
176 KernelVersion: v5.14 83 KernelVersion: v5.14
177 Contact: linux-cxl@vger.kernel.org 84 Contact: linux-cxl@vger.kernel.org
178 Description: 85 Description:
179 (RO) CXL port objects are enum 86 (RO) CXL port objects are enumerated from either a platform
180 firmware device (ACPI0017 and 87 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
181 port with CXL component regist 88 port with CXL component registers. The 'uport' symlink connects
182 the CXL portX object to the de 89 the CXL portX object to the device that published the CXL port
183 capability. 90 capability.
184 91
185 92
186 What: /sys/bus/cxl/devices/{port,end 93 What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport
187 Date: January, 2023 94 Date: January, 2023
188 KernelVersion: v6.3 95 KernelVersion: v6.3
189 Contact: linux-cxl@vger.kernel.org 96 Contact: linux-cxl@vger.kernel.org
190 Description: 97 Description:
191 (RO) CXL port objects are inst 98 (RO) CXL port objects are instantiated for each upstream port in
192 a CXL/PCIe switch, and for eac 99 a CXL/PCIe switch, and for each endpoint to map the
193 corresponding memory device in 100 corresponding memory device into the CXL port hierarchy. When a
194 descendant CXL port (switch or 101 descendant CXL port (switch or endpoint) is enumerated it is
195 useful to know which 'dport' o 102 useful to know which 'dport' object in the parent CXL port
196 routes to this descendant. The 103 routes to this descendant. The 'parent_dport' symlink points to
197 the device representing the do 104 the device representing the downstream port of a CXL switch that
198 routes to {port,endpoint}X. 105 routes to {port,endpoint}X.
199 106
200 107
201 What: /sys/bus/cxl/devices/portX/dpo 108 What: /sys/bus/cxl/devices/portX/dportY
202 Date: June, 2021 109 Date: June, 2021
203 KernelVersion: v5.14 110 KernelVersion: v5.14
204 Contact: linux-cxl@vger.kernel.org 111 Contact: linux-cxl@vger.kernel.org
205 Description: 112 Description:
206 (RO) CXL port objects are enum 113 (RO) CXL port objects are enumerated from either a platform
207 firmware device (ACPI0017 and 114 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
208 port with CXL component regist 115 port with CXL component registers. The 'dportY' symlink
209 identifies one or more downstr 116 identifies one or more downstream ports that the upstream port
210 may target in its decode of CX 117 may target in its decode of CXL memory resources. The 'Y'
211 integer reflects the hardware 118 integer reflects the hardware port unique-id used in the
212 hardware decoder target list. 119 hardware decoder target list.
213 120
214 121
215 What: /sys/bus/cxl/devices/portX/dec <<
216 Date: October, 2023 <<
217 KernelVersion: v6.7 <<
218 Contact: linux-cxl@vger.kernel.org <<
219 Description: <<
220 (RO) A memory device is consid <<
221 decoders are in the "committed <<
222 CXL HDM Decoder n Control Regi <<
223 operations like "sanitize" are <<
224 decoding a Host Physical Addre <<
225 may be elevated without any re <<
226 enumerated, as this may be due <<
227 platform firwmare or a previou <<
228 <<
229 <<
230 What: /sys/bus/cxl/devices/decoderX. 122 What: /sys/bus/cxl/devices/decoderX.Y
231 Date: June, 2021 123 Date: June, 2021
232 KernelVersion: v5.14 124 KernelVersion: v5.14
233 Contact: linux-cxl@vger.kernel.org 125 Contact: linux-cxl@vger.kernel.org
234 Description: 126 Description:
235 (RO) CXL decoder objects are e 127 (RO) CXL decoder objects are enumerated from either a platform
236 firmware description, or a CXL 128 firmware description, or a CXL HDM decoder register set in a
237 PCIe device (see CXL 2.0 secti 129 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
238 Capability Structure). The 'X' 130 Capability Structure). The 'X' in decoderX.Y represents the
239 cxl_port container of this dec 131 cxl_port container of this decoder, and 'Y' represents the
240 instance id of a given decoder 132 instance id of a given decoder resource.
241 133
242 134
243 What: /sys/bus/cxl/devices/decoderX. 135 What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
244 Date: June, 2021 136 Date: June, 2021
245 KernelVersion: v5.14 137 KernelVersion: v5.14
246 Contact: linux-cxl@vger.kernel.org 138 Contact: linux-cxl@vger.kernel.org
247 Description: 139 Description:
248 (RO) The 'start' and 'size' at 140 (RO) The 'start' and 'size' attributes together convey the
249 physical address base and numb 141 physical address base and number of bytes mapped in the
250 decoder's decode window. For d 142 decoder's decode window. For decoders of devtype
251 "cxl_decoder_root" the address 143 "cxl_decoder_root" the address range is fixed. For decoders of
252 devtype "cxl_decoder_switch" t 144 devtype "cxl_decoder_switch" the address is bounded by the
253 decode range of the cxl_port a 145 decode range of the cxl_port ancestor of the decoder's cxl_port,
254 and dynamically updates based 146 and dynamically updates based on the active memory regions in
255 that address space. 147 that address space.
256 148
257 149
258 What: /sys/bus/cxl/devices/decoderX. 150 What: /sys/bus/cxl/devices/decoderX.Y/locked
259 Date: June, 2021 151 Date: June, 2021
260 KernelVersion: v5.14 152 KernelVersion: v5.14
261 Contact: linux-cxl@vger.kernel.org 153 Contact: linux-cxl@vger.kernel.org
262 Description: 154 Description:
263 (RO) CXL HDM decoders have the 155 (RO) CXL HDM decoders have the capability to lock the
264 configuration until the next d 156 configuration until the next device reset. For decoders of
265 devtype "cxl_decoder_root" the 157 devtype "cxl_decoder_root" there is no standard facility to
266 unlock them. For decoders of 158 unlock them. For decoders of devtype "cxl_decoder_switch" a
267 secondary bus reset, of the PC 159 secondary bus reset, of the PCIe bridge that provides the bus
268 for this decoders uport, unloc 160 for this decoders uport, unlocks / resets the decoder.
269 161
270 162
271 What: /sys/bus/cxl/devices/decoderX. 163 What: /sys/bus/cxl/devices/decoderX.Y/target_list
272 Date: June, 2021 164 Date: June, 2021
273 KernelVersion: v5.14 165 KernelVersion: v5.14
274 Contact: linux-cxl@vger.kernel.org 166 Contact: linux-cxl@vger.kernel.org
275 Description: 167 Description:
276 (RO) Display a comma separated 168 (RO) Display a comma separated list of the current decoder
277 target configuration. The list 169 target configuration. The list is ordered by the current
278 configured interleave order of 170 configured interleave order of the decoder's dport instances.
279 Each entry in the list is a dp 171 Each entry in the list is a dport id.
280 172
281 173
282 What: /sys/bus/cxl/devices/decoderX. 174 What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
283 Date: June, 2021 175 Date: June, 2021
284 KernelVersion: v5.14 176 KernelVersion: v5.14
285 Contact: linux-cxl@vger.kernel.org 177 Contact: linux-cxl@vger.kernel.org
286 Description: 178 Description:
287 (RO) When a CXL decoder is of 179 (RO) When a CXL decoder is of devtype "cxl_decoder_root", it
288 represents a fixed memory wind 180 represents a fixed memory window identified by platform
289 firmware. A fixed window may o 181 firmware. A fixed window may only support a subset of memory
290 types. The 'cap_*' attributes 182 types. The 'cap_*' attributes indicate whether persistent
291 memory, volatile memory, accel 183 memory, volatile memory, accelerator memory, and / or expander
292 memory may be mapped behind th 184 memory may be mapped behind this decoder's memory window.
293 185
294 186
295 What: /sys/bus/cxl/devices/decoderX. 187 What: /sys/bus/cxl/devices/decoderX.Y/target_type
296 Date: June, 2021 188 Date: June, 2021
297 KernelVersion: v5.14 189 KernelVersion: v5.14
298 Contact: linux-cxl@vger.kernel.org 190 Contact: linux-cxl@vger.kernel.org
299 Description: 191 Description:
300 (RO) When a CXL decoder is of 192 (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it
301 can optionally decode either a 193 can optionally decode either accelerator memory (type-2) or
302 expander memory (type-3). The 194 expander memory (type-3). The 'target_type' attribute indicates
303 the current setting which may 195 the current setting which may dynamically change based on what
304 memory regions are activated i 196 memory regions are activated in this decode hierarchy.
305 197
306 198
307 What: /sys/bus/cxl/devices/endpointX 199 What: /sys/bus/cxl/devices/endpointX/CDAT
308 Date: July, 2022 200 Date: July, 2022
309 KernelVersion: v6.0 201 KernelVersion: v6.0
310 Contact: linux-cxl@vger.kernel.org 202 Contact: linux-cxl@vger.kernel.org
311 Description: 203 Description:
312 (RO) If this sysfs entry is no 204 (RO) If this sysfs entry is not present no DOE mailbox was
313 found to support CDAT data. I 205 found to support CDAT data. If it is present and the length of
314 the data is 0 reading the CDAT 206 the data is 0 reading the CDAT data failed. Otherwise the CDAT
315 data is reported. 207 data is reported.
316 208
317 209
318 What: /sys/bus/cxl/devices/decoderX. 210 What: /sys/bus/cxl/devices/decoderX.Y/mode
319 Date: May, 2022 211 Date: May, 2022
320 KernelVersion: v6.0 212 KernelVersion: v6.0
321 Contact: linux-cxl@vger.kernel.org 213 Contact: linux-cxl@vger.kernel.org
322 Description: 214 Description:
323 (RW) When a CXL decoder is of 215 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
324 translates from a host physica 216 translates from a host physical address range, to a device local
325 address range. Device-local ad 217 address range. Device-local address ranges are further split
326 into a 'ram' (volatile memory) 218 into a 'ram' (volatile memory) range and 'pmem' (persistent
327 memory) range. The 'mode' attr 219 memory) range. The 'mode' attribute emits one of 'ram', 'pmem',
328 'mixed', or 'none'. The 'mixed 220 'mixed', or 'none'. The 'mixed' indication is for error cases
329 when a decoder straddles the v 221 when a decoder straddles the volatile/persistent partition
330 boundary, and 'none' indicates 222 boundary, and 'none' indicates the decoder is not actively
331 decoding, or no DPA allocation 223 decoding, or no DPA allocation policy has been set.
332 224
333 'mode' can be written, when th 225 'mode' can be written, when the decoder is in the 'disabled'
334 state, with either 'ram' or 'p 226 state, with either 'ram' or 'pmem' to set the boundaries for the
335 next allocation. 227 next allocation.
336 228
337 229
338 What: /sys/bus/cxl/devices/decoderX. 230 What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource
339 Date: May, 2022 231 Date: May, 2022
340 KernelVersion: v6.0 232 KernelVersion: v6.0
341 Contact: linux-cxl@vger.kernel.org 233 Contact: linux-cxl@vger.kernel.org
342 Description: 234 Description:
343 (RO) When a CXL decoder is of 235 (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",
344 and its 'dpa_size' attribute i 236 and its 'dpa_size' attribute is non-zero, this attribute
345 indicates the device physical 237 indicates the device physical address (DPA) base address of the
346 allocation. 238 allocation.
347 239
348 240
349 What: /sys/bus/cxl/devices/decoderX. 241 What: /sys/bus/cxl/devices/decoderX.Y/dpa_size
350 Date: May, 2022 242 Date: May, 2022
351 KernelVersion: v6.0 243 KernelVersion: v6.0
352 Contact: linux-cxl@vger.kernel.org 244 Contact: linux-cxl@vger.kernel.org
353 Description: 245 Description:
354 (RW) When a CXL decoder is of 246 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
355 translates from a host physica 247 translates from a host physical address range, to a device local
356 address range. The range, base 248 address range. The range, base address plus length in bytes, of
357 DPA allocated to this decoder 249 DPA allocated to this decoder is conveyed in these 2 attributes.
358 Allocations can be mutated as 250 Allocations can be mutated as long as the decoder is in the
359 disabled state. A write to 'dp 251 disabled state. A write to 'dpa_size' releases the previous DPA
360 allocation and then attempts t 252 allocation and then attempts to allocate from the free capacity
361 in the device partition referr 253 in the device partition referred to by 'decoderX.Y/mode'.
362 Allocate and free requests can 254 Allocate and free requests can only be performed on the highest
363 instance number disabled decod 255 instance number disabled decoder with non-zero size. I.e.
364 allocations are enforced to oc 256 allocations are enforced to occur in increasing 'decoderX.Y/id'
365 order and frees are enforced t 257 order and frees are enforced to occur in decreasing
366 'decoderX.Y/id' order. 258 'decoderX.Y/id' order.
367 259
368 260
369 What: /sys/bus/cxl/devices/decoderX. 261 What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways
370 Date: May, 2022 262 Date: May, 2022
371 KernelVersion: v6.0 263 KernelVersion: v6.0
372 Contact: linux-cxl@vger.kernel.org 264 Contact: linux-cxl@vger.kernel.org
373 Description: 265 Description:
374 (RO) The number of targets acr 266 (RO) The number of targets across which this decoder's host
375 physical address (HPA) memory 267 physical address (HPA) memory range is interleaved. The device
376 maps every Nth block of HPA (o 268 maps every Nth block of HPA (of size ==
377 'interleave_granularity') to c 269 'interleave_granularity') to consecutive DPA addresses. The
378 decoder's position in the inte 270 decoder's position in the interleave is determined by the
379 device's (endpoint or switch) 271 device's (endpoint or switch) switch ancestry. For root
380 decoders their interleave is s 272 decoders their interleave is specified by platform firmware and
381 they only specify a downstream 273 they only specify a downstream target order for host bridges.
382 274
383 275
384 What: /sys/bus/cxl/devices/decoderX. 276 What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity
385 Date: May, 2022 277 Date: May, 2022
386 KernelVersion: v6.0 278 KernelVersion: v6.0
387 Contact: linux-cxl@vger.kernel.org 279 Contact: linux-cxl@vger.kernel.org
388 Description: 280 Description:
389 (RO) The number of consecutive 281 (RO) The number of consecutive bytes of host physical address
390 space this decoder claims at a 282 space this decoder claims at address N before the decode rotates
391 to the next target in the inte 283 to the next target in the interleave at address N +
392 interleave_granularity (assumi 284 interleave_granularity (assuming N is aligned to
393 interleave_granularity). 285 interleave_granularity).
394 286
395 287
396 What: /sys/bus/cxl/devices/decoderX. 288 What: /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region
397 Date: May, 2022, January, 2023 289 Date: May, 2022, January, 2023
398 KernelVersion: v6.0 (pmem), v6.3 (ram) 290 KernelVersion: v6.0 (pmem), v6.3 (ram)
399 Contact: linux-cxl@vger.kernel.org 291 Contact: linux-cxl@vger.kernel.org
400 Description: 292 Description:
401 (RW) Write a string in the for 293 (RW) Write a string in the form 'regionZ' to start the process
402 of defining a new persistent, 294 of defining a new persistent, or volatile memory region
403 (interleave-set) within the de 295 (interleave-set) within the decode range bounded by root decoder
404 'decoderX.Y'. The value writte 296 'decoderX.Y'. The value written must match the current value
405 returned from reading this att 297 returned from reading this attribute. An atomic compare exchange
406 operation is done on write to 298 operation is done on write to assign the requested id to a
407 region and allocate the region 299 region and allocate the region-id for the next creation attempt.
408 EBUSY is returned if the regio 300 EBUSY is returned if the region name written does not match the
409 current cached value. 301 current cached value.
410 302
411 303
412 What: /sys/bus/cxl/devices/decoderX. 304 What: /sys/bus/cxl/devices/decoderX.Y/delete_region
413 Date: May, 2022 305 Date: May, 2022
414 KernelVersion: v6.0 306 KernelVersion: v6.0
415 Contact: linux-cxl@vger.kernel.org 307 Contact: linux-cxl@vger.kernel.org
416 Description: 308 Description:
417 (WO) Write a string in the for 309 (WO) Write a string in the form 'regionZ' to delete that region,
418 provided it is currently idle 310 provided it is currently idle / not bound to a driver.
419 311
420 312
421 What: /sys/bus/cxl/devices/decoderX. <<
422 Date: May, 2023 <<
423 KernelVersion: v6.5 <<
424 Contact: linux-cxl@vger.kernel.org <<
425 Description: <<
426 (RO) For CXL host platforms th <<
427 root-decoder-only attribute co <<
428 that identifies a QoS performa <<
429 This class-id can be compared <<
430 published for each memory-type <<
431 it is not required that endpoi <<
432 to a matching platform class, <<
433 there are platform specific si <<
434 <<
435 <<
436 What: /sys/bus/cxl/devices/regionZ/u 313 What: /sys/bus/cxl/devices/regionZ/uuid
437 Date: May, 2022 314 Date: May, 2022
438 KernelVersion: v6.0 315 KernelVersion: v6.0
439 Contact: linux-cxl@vger.kernel.org 316 Contact: linux-cxl@vger.kernel.org
440 Description: 317 Description:
441 (RW) Write a unique identifier 318 (RW) Write a unique identifier for the region. This field must
442 be set for persistent regions 319 be set for persistent regions and it must not conflict with the
443 UUID of another region. For vo 320 UUID of another region. For volatile ram regions this
444 attribute is a read-only empty 321 attribute is a read-only empty string.
445 322
446 323
447 What: /sys/bus/cxl/devices/regionZ/i 324 What: /sys/bus/cxl/devices/regionZ/interleave_granularity
448 Date: May, 2022 325 Date: May, 2022
449 KernelVersion: v6.0 326 KernelVersion: v6.0
450 Contact: linux-cxl@vger.kernel.org 327 Contact: linux-cxl@vger.kernel.org
451 Description: 328 Description:
452 (RW) Set the number of consecu 329 (RW) Set the number of consecutive bytes each device in the
453 interleave set will claim. The 330 interleave set will claim. The possible interleave granularity
454 values are determined by the C 331 values are determined by the CXL spec and the participating
455 devices. 332 devices.
456 333
457 334
458 What: /sys/bus/cxl/devices/regionZ/i 335 What: /sys/bus/cxl/devices/regionZ/interleave_ways
459 Date: May, 2022 336 Date: May, 2022
460 KernelVersion: v6.0 337 KernelVersion: v6.0
461 Contact: linux-cxl@vger.kernel.org 338 Contact: linux-cxl@vger.kernel.org
462 Description: 339 Description:
463 (RW) Configures the number of 340 (RW) Configures the number of devices participating in the
464 region is set by writing this 341 region is set by writing this value. Each device will provide
465 1/interleave_ways of storage f 342 1/interleave_ways of storage for the region.
466 343
467 344
468 What: /sys/bus/cxl/devices/regionZ/s 345 What: /sys/bus/cxl/devices/regionZ/size
469 Date: May, 2022 346 Date: May, 2022
470 KernelVersion: v6.0 347 KernelVersion: v6.0
471 Contact: linux-cxl@vger.kernel.org 348 Contact: linux-cxl@vger.kernel.org
472 Description: 349 Description:
473 (RW) System physical address s 350 (RW) System physical address space to be consumed by the region.
474 When written trigger the drive 351 When written trigger the driver to allocate space out of the
475 parent root decoder's address 352 parent root decoder's address space. When read the size of the
476 address space is reported and 353 address space is reported and should match the span of the
477 region's resource attribute. S 354 region's resource attribute. Size shall be set after the
478 interleave configuration param 355 interleave configuration parameters. Once set it cannot be
479 changed, only freed by writing 356 changed, only freed by writing 0. The kernel makes no guarantees
480 that data is maintained over a 357 that data is maintained over an address space freeing event, and
481 there is no guarantee that a f 358 there is no guarantee that a free followed by an allocate
482 results in the same address be 359 results in the same address being allocated.
483 360
484 361
485 What: /sys/bus/cxl/devices/regionZ/m 362 What: /sys/bus/cxl/devices/regionZ/mode
486 Date: January, 2023 363 Date: January, 2023
487 KernelVersion: v6.3 364 KernelVersion: v6.3
488 Contact: linux-cxl@vger.kernel.org 365 Contact: linux-cxl@vger.kernel.org
489 Description: 366 Description:
490 (RO) The mode of a region is e 367 (RO) The mode of a region is established at region creation time
491 and dictates the mode of the e 368 and dictates the mode of the endpoint decoder that comprise the
492 region. For more details on th 369 region. For more details on the possible modes see
493 /sys/bus/cxl/devices/decoderX. 370 /sys/bus/cxl/devices/decoderX.Y/mode
494 371
495 372
496 What: /sys/bus/cxl/devices/regionZ/r 373 What: /sys/bus/cxl/devices/regionZ/resource
497 Date: May, 2022 374 Date: May, 2022
498 KernelVersion: v6.0 375 KernelVersion: v6.0
499 Contact: linux-cxl@vger.kernel.org 376 Contact: linux-cxl@vger.kernel.org
500 Description: 377 Description:
501 (RO) A region is a contiguous 378 (RO) A region is a contiguous partition of a CXL root decoder
502 address space. Region capacity 379 address space. Region capacity is allocated by writing to the
503 size attribute, the resulting 380 size attribute, the resulting physical address space determined
504 by the driver is reflected her 381 by the driver is reflected here. It is therefore not useful to
505 read this before writing a val 382 read this before writing a value to the size attribute.
506 383
507 384
508 What: /sys/bus/cxl/devices/regionZ/t 385 What: /sys/bus/cxl/devices/regionZ/target[0..N]
509 Date: May, 2022 386 Date: May, 2022
510 KernelVersion: v6.0 387 KernelVersion: v6.0
511 Contact: linux-cxl@vger.kernel.org 388 Contact: linux-cxl@vger.kernel.org
512 Description: 389 Description:
513 (RW) Write an endpoint decoder 390 (RW) Write an endpoint decoder object name to 'targetX' where X
514 is the intended position of th 391 is the intended position of the endpoint device in the region
515 interleave and N is the 'inter 392 interleave and N is the 'interleave_ways' setting for the
516 region. ENXIO is returned if t 393 region. ENXIO is returned if the write results in an impossible
517 to map decode scenario, like t 394 to map decode scenario, like the endpoint is unreachable at that
518 position relative to the root 395 position relative to the root decoder interleave. EBUSY is
519 returned if the position in th 396 returned if the position in the region is already occupied, or
520 if the region is not in a stat 397 if the region is not in a state to accept interleave
521 configuration changes. EINVAL 398 configuration changes. EINVAL is returned if the object name is
522 not an endpoint decoder. Once 399 not an endpoint decoder. Once all positions have been
523 successfully written a final v 400 successfully written a final validation for decode conflicts is
524 performed before activating th 401 performed before activating the region.
525 402
526 403
527 What: /sys/bus/cxl/devices/regionZ/c 404 What: /sys/bus/cxl/devices/regionZ/commit
528 Date: May, 2022 405 Date: May, 2022
529 KernelVersion: v6.0 406 KernelVersion: v6.0
530 Contact: linux-cxl@vger.kernel.org 407 Contact: linux-cxl@vger.kernel.org
531 Description: 408 Description:
532 (RW) Write a boolean 'true' st 409 (RW) Write a boolean 'true' string value to this attribute to
533 trigger the region to transiti 410 trigger the region to transition from the software programmed
534 state to the actively decoding 411 state to the actively decoding in hardware state. The commit
535 operation in addition to valid 412 operation in addition to validating that the region is in proper
536 configured state, validates th 413 configured state, validates that the decoders are being
537 committed in spec mandated ord 414 committed in spec mandated order (last committed decoder id +
538 1), and checks that the hardwa 415 1), and checks that the hardware accepts the commit request.
539 Reading this value indicates w 416 Reading this value indicates whether the region is committed or
540 not. 417 not.
541 <<
542 <<
543 What: /sys/bus/cxl/devices/memX/trig <<
544 Date: April, 2023 <<
545 KernelVersion: v6.4 <<
546 Contact: linux-cxl@vger.kernel.org <<
547 Description: <<
548 (WO) When a boolean 'true' is <<
549 memdev driver retrieves the po <<
550 list consists of addresses tha <<
551 in poison if accessed, and the <<
552 attribute is only visible for <<
553 capability. The retrieved erro <<
554 events when cxl_poison event t <<
555 <<
556 <<
557 What: /sys/bus/cxl/devices/regionZ/a <<
558 /sys/bus/cxl/devices/regionZ/a <<
559 Date: Jan, 2024 <<
560 KernelVersion: v6.9 <<
561 Contact: linux-cxl@vger.kernel.org <<
562 Description: <<
563 (RO) The aggregated read or wr <<
564 number is the accumulated read <<
565 devices that contributes to th <<
566 identical data that should app <<
567 /sys/devices/system/node/nodeX <<
568 /sys/devices/system/node/nodeX <<
569 See Documentation/ABI/stable/s <<
570 the number to the closest init <<
571 number to the closest CPU. <<
572 <<
573 <<
574 What: /sys/bus/cxl/devices/regionZ/a <<
575 /sys/bus/cxl/devices/regionZ/a <<
576 Date: Jan, 2024 <<
577 KernelVersion: v6.9 <<
578 Contact: linux-cxl@vger.kernel.org <<
579 Description: <<
580 (RO) The read or write latency <<
581 the worst read or write latenc <<
582 contributes to the region in n <<
583 that should appear in <<
584 /sys/devices/system/node/nodeX <<
585 /sys/devices/system/node/nodeX <<
586 See Documentation/ABI/stable/s <<
587 the number to the closest init <<
588 number to the closest CPU. <<
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