1 What: /sys/bus/cxl/flush 1 What: /sys/bus/cxl/flush
2 Date: Januarry, 2022 2 Date: Januarry, 2022
3 KernelVersion: v5.18 3 KernelVersion: v5.18
4 Contact: linux-cxl@vger.kernel.org 4 Contact: linux-cxl@vger.kernel.org
5 Description: 5 Description:
6 (WO) If userspace manually unb 6 (WO) If userspace manually unbinds a port the kernel schedules
7 all descendant memdevs for unb 7 all descendant memdevs for unbind. Writing '1' to this attribute
8 flushes that work. 8 flushes that work.
9 9
10 10
11 What: /sys/bus/cxl/devices/memX/firm 11 What: /sys/bus/cxl/devices/memX/firmware_version
12 Date: December, 2020 12 Date: December, 2020
13 KernelVersion: v5.12 13 KernelVersion: v5.12
14 Contact: linux-cxl@vger.kernel.org 14 Contact: linux-cxl@vger.kernel.org
15 Description: 15 Description:
16 (RO) "FW Revision" string as r 16 (RO) "FW Revision" string as reported by the Identify
17 Memory Device Output Payload i 17 Memory Device Output Payload in the CXL-2.0
18 specification. 18 specification.
19 19
20 20
21 What: /sys/bus/cxl/devices/memX/ram/ 21 What: /sys/bus/cxl/devices/memX/ram/size
22 Date: December, 2020 22 Date: December, 2020
23 KernelVersion: v5.12 23 KernelVersion: v5.12
24 Contact: linux-cxl@vger.kernel.org 24 Contact: linux-cxl@vger.kernel.org
25 Description: 25 Description:
26 (RO) "Volatile Only Capacity" 26 (RO) "Volatile Only Capacity" as bytes. Represents the
27 identically named field in the 27 identically named field in the Identify Memory Device Output
28 Payload in the CXL-2.0 specifi 28 Payload in the CXL-2.0 specification.
29 29
30 30
31 What: /sys/bus/cxl/devices/memX/ram/ <<
32 Date: May, 2023 <<
33 KernelVersion: v6.8 <<
34 Contact: linux-cxl@vger.kernel.org <<
35 Description: <<
36 (RO) For CXL host platforms th <<
37 this attribute conveys a comma <<
38 specific cookies that identifi <<
39 for the volatile partition of <<
40 class-ids can be compared agai <<
41 published for a root decoder. <<
42 that the endpoints map their l <<
43 matching platform class, misma <<
44 and there are platform specifi <<
45 side-effects that may result. <<
46 <<
47 <<
48 What: /sys/bus/cxl/devices/memX/pmem 31 What: /sys/bus/cxl/devices/memX/pmem/size
49 Date: December, 2020 32 Date: December, 2020
50 KernelVersion: v5.12 33 KernelVersion: v5.12
51 Contact: linux-cxl@vger.kernel.org 34 Contact: linux-cxl@vger.kernel.org
52 Description: 35 Description:
53 (RO) "Persistent Only Capacity 36 (RO) "Persistent Only Capacity" as bytes. Represents the
54 identically named field in the 37 identically named field in the Identify Memory Device Output
55 Payload in the CXL-2.0 specifi 38 Payload in the CXL-2.0 specification.
56 39
57 40
58 What: /sys/bus/cxl/devices/memX/pmem <<
59 Date: May, 2023 <<
60 KernelVersion: v6.8 <<
61 Contact: linux-cxl@vger.kernel.org <<
62 Description: <<
63 (RO) For CXL host platforms th <<
64 this attribute conveys a comma <<
65 specific cookies that identifi <<
66 for the persistent partition o <<
67 class-ids can be compared agai <<
68 published for a root decoder. <<
69 that the endpoints map their l <<
70 matching platform class, misma <<
71 and there are platform specifi <<
72 side-effects that may result. <<
73 <<
74 <<
75 What: /sys/bus/cxl/devices/memX/seri 41 What: /sys/bus/cxl/devices/memX/serial
76 Date: January, 2022 42 Date: January, 2022
77 KernelVersion: v5.18 43 KernelVersion: v5.18
78 Contact: linux-cxl@vger.kernel.org 44 Contact: linux-cxl@vger.kernel.org
79 Description: 45 Description:
80 (RO) 64-bit serial number per 46 (RO) 64-bit serial number per the PCIe Device Serial Number
81 capability. Mandatory for CXL 47 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
82 Memory Device PCIe Capabilitie 48 Memory Device PCIe Capabilities and Extended Capabilities.
83 49
84 50
85 What: /sys/bus/cxl/devices/memX/numa 51 What: /sys/bus/cxl/devices/memX/numa_node
86 Date: January, 2022 52 Date: January, 2022
87 KernelVersion: v5.18 53 KernelVersion: v5.18
88 Contact: linux-cxl@vger.kernel.org 54 Contact: linux-cxl@vger.kernel.org
89 Description: 55 Description:
90 (RO) If NUMA is enabled and th 56 (RO) If NUMA is enabled and the platform has affinitized the
91 host PCI device for this memor 57 host PCI device for this memory device, emit the CPU node
92 affinity for this device. 58 affinity for this device.
93 59
94 60
95 What: /sys/bus/cxl/devices/memX/secu 61 What: /sys/bus/cxl/devices/memX/security/state
96 Date: June, 2023 62 Date: June, 2023
97 KernelVersion: v6.5 63 KernelVersion: v6.5
98 Contact: linux-cxl@vger.kernel.org 64 Contact: linux-cxl@vger.kernel.org
99 Description: 65 Description:
100 (RO) Reading this file will di 66 (RO) Reading this file will display the CXL security state for
101 that device. Such states can b 67 that device. Such states can be: 'disabled', 'sanitize', when
102 a sanitization is currently un 68 a sanitization is currently underway; or those available only
103 for persistent memory: 'locked 69 for persistent memory: 'locked', 'unlocked' or 'frozen'. This
104 sysfs entry is select/poll cap 70 sysfs entry is select/poll capable from userspace to notify
105 upon completion of a sanitize 71 upon completion of a sanitize operation.
106 72
107 73
108 What: /sys/bus/cxl/devices/memX/secu 74 What: /sys/bus/cxl/devices/memX/security/sanitize
109 Date: June, 2023 75 Date: June, 2023
110 KernelVersion: v6.5 76 KernelVersion: v6.5
111 Contact: linux-cxl@vger.kernel.org 77 Contact: linux-cxl@vger.kernel.org
112 Description: 78 Description:
113 (WO) Write a boolean 'true' st 79 (WO) Write a boolean 'true' string value to this attribute to
114 sanitize the device to securel 80 sanitize the device to securely re-purpose or decommission it.
115 This is done by ensuring that 81 This is done by ensuring that all user data and meta-data,
116 whether it resides in persiste 82 whether it resides in persistent capacity, volatile capacity,
117 or the LSA, is made permanentl 83 or the LSA, is made permanently unavailable by whatever means
118 is appropriate for the media t 84 is appropriate for the media type. This functionality requires
119 the device to be disabled, tha 85 the device to be disabled, that is, not actively decoding any
120 HPA ranges. This permits avoid 86 HPA ranges. This permits avoiding explicit global CPU cache
121 management, relying instead fo 87 management, relying instead for it to be done when a region
122 transitions between software p 88 transitions between software programmed and hardware committed
123 states. If this file is not pr 89 states. If this file is not present, then there is no hardware
124 support for the operation. 90 support for the operation.
125 91
126 92
127 What /sys/bus/cxl/devices/memX/secu 93 What /sys/bus/cxl/devices/memX/security/erase
128 Date: June, 2023 94 Date: June, 2023
129 KernelVersion: v6.5 95 KernelVersion: v6.5
130 Contact: linux-cxl@vger.kernel.org 96 Contact: linux-cxl@vger.kernel.org
131 Description: 97 Description:
132 (WO) Write a boolean 'true' st 98 (WO) Write a boolean 'true' string value to this attribute to
133 secure erase user data by chan 99 secure erase user data by changing the media encryption keys for
134 all user data areas of the dev 100 all user data areas of the device. This functionality requires
135 the device to be disabled, tha 101 the device to be disabled, that is, not actively decoding any
136 HPA ranges. This permits avoid 102 HPA ranges. This permits avoiding explicit global CPU cache
137 management, relying instead fo 103 management, relying instead for it to be done when a region
138 transitions between software p 104 transitions between software programmed and hardware committed
139 states. If this file is not pr 105 states. If this file is not present, then there is no hardware
140 support for the operation. 106 support for the operation.
141 107
142 108
143 What: /sys/bus/cxl/devices/memX/firm 109 What: /sys/bus/cxl/devices/memX/firmware/
144 Date: April, 2023 110 Date: April, 2023
145 KernelVersion: v6.5 111 KernelVersion: v6.5
146 Contact: linux-cxl@vger.kernel.org 112 Contact: linux-cxl@vger.kernel.org
147 Description: 113 Description:
148 (RW) Firmware uploader mechani 114 (RW) Firmware uploader mechanism. The different files under
149 this directory can be used to 115 this directory can be used to upload and activate new
150 firmware for CXL devices. The 116 firmware for CXL devices. The interfaces under this are
151 documented in sysfs-class-firm 117 documented in sysfs-class-firmware.
152 118
153 119
154 What: /sys/bus/cxl/devices/*/devtype 120 What: /sys/bus/cxl/devices/*/devtype
155 Date: June, 2021 121 Date: June, 2021
156 KernelVersion: v5.14 122 KernelVersion: v5.14
157 Contact: linux-cxl@vger.kernel.org 123 Contact: linux-cxl@vger.kernel.org
158 Description: 124 Description:
159 (RO) CXL device objects export 125 (RO) CXL device objects export the devtype attribute which
160 mirrors the same value communi 126 mirrors the same value communicated in the DEVTYPE environment
161 variable for uevents for devic 127 variable for uevents for devices on the "cxl" bus.
162 128
163 129
164 What: /sys/bus/cxl/devices/*/modalia 130 What: /sys/bus/cxl/devices/*/modalias
165 Date: December, 2021 131 Date: December, 2021
166 KernelVersion: v5.18 132 KernelVersion: v5.18
167 Contact: linux-cxl@vger.kernel.org 133 Contact: linux-cxl@vger.kernel.org
168 Description: 134 Description:
169 (RO) CXL device objects export 135 (RO) CXL device objects export the modalias attribute which
170 mirrors the same value communi 136 mirrors the same value communicated in the MODALIAS environment
171 variable for uevents for devic 137 variable for uevents for devices on the "cxl" bus.
172 138
173 139
174 What: /sys/bus/cxl/devices/portX/upo 140 What: /sys/bus/cxl/devices/portX/uport
175 Date: June, 2021 141 Date: June, 2021
176 KernelVersion: v5.14 142 KernelVersion: v5.14
177 Contact: linux-cxl@vger.kernel.org 143 Contact: linux-cxl@vger.kernel.org
178 Description: 144 Description:
179 (RO) CXL port objects are enum 145 (RO) CXL port objects are enumerated from either a platform
180 firmware device (ACPI0017 and 146 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
181 port with CXL component regist 147 port with CXL component registers. The 'uport' symlink connects
182 the CXL portX object to the de 148 the CXL portX object to the device that published the CXL port
183 capability. 149 capability.
184 150
185 151
186 What: /sys/bus/cxl/devices/{port,end 152 What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport
187 Date: January, 2023 153 Date: January, 2023
188 KernelVersion: v6.3 154 KernelVersion: v6.3
189 Contact: linux-cxl@vger.kernel.org 155 Contact: linux-cxl@vger.kernel.org
190 Description: 156 Description:
191 (RO) CXL port objects are inst 157 (RO) CXL port objects are instantiated for each upstream port in
192 a CXL/PCIe switch, and for eac 158 a CXL/PCIe switch, and for each endpoint to map the
193 corresponding memory device in 159 corresponding memory device into the CXL port hierarchy. When a
194 descendant CXL port (switch or 160 descendant CXL port (switch or endpoint) is enumerated it is
195 useful to know which 'dport' o 161 useful to know which 'dport' object in the parent CXL port
196 routes to this descendant. The 162 routes to this descendant. The 'parent_dport' symlink points to
197 the device representing the do 163 the device representing the downstream port of a CXL switch that
198 routes to {port,endpoint}X. 164 routes to {port,endpoint}X.
199 165
200 166
201 What: /sys/bus/cxl/devices/portX/dpo 167 What: /sys/bus/cxl/devices/portX/dportY
202 Date: June, 2021 168 Date: June, 2021
203 KernelVersion: v5.14 169 KernelVersion: v5.14
204 Contact: linux-cxl@vger.kernel.org 170 Contact: linux-cxl@vger.kernel.org
205 Description: 171 Description:
206 (RO) CXL port objects are enum 172 (RO) CXL port objects are enumerated from either a platform
207 firmware device (ACPI0017 and 173 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
208 port with CXL component regist 174 port with CXL component registers. The 'dportY' symlink
209 identifies one or more downstr 175 identifies one or more downstream ports that the upstream port
210 may target in its decode of CX 176 may target in its decode of CXL memory resources. The 'Y'
211 integer reflects the hardware 177 integer reflects the hardware port unique-id used in the
212 hardware decoder target list. 178 hardware decoder target list.
213 179
214 180
215 What: /sys/bus/cxl/devices/portX/dec 181 What: /sys/bus/cxl/devices/portX/decoders_committed
216 Date: October, 2023 182 Date: October, 2023
217 KernelVersion: v6.7 183 KernelVersion: v6.7
218 Contact: linux-cxl@vger.kernel.org 184 Contact: linux-cxl@vger.kernel.org
219 Description: 185 Description:
220 (RO) A memory device is consid 186 (RO) A memory device is considered active when any of its
221 decoders are in the "committed 187 decoders are in the "committed" state (See CXL 3.0 8.2.4.19.7
222 CXL HDM Decoder n Control Regi 188 CXL HDM Decoder n Control Register). Hotplug and destructive
223 operations like "sanitize" are 189 operations like "sanitize" are blocked while device is actively
224 decoding a Host Physical Addre 190 decoding a Host Physical Address range. Note that this number
225 may be elevated without any re 191 may be elevated without any regionX objects active or even
226 enumerated, as this may be due 192 enumerated, as this may be due to decoders established by
227 platform firwmare or a previou 193 platform firwmare or a previous kernel (kexec).
228 194
229 195
230 What: /sys/bus/cxl/devices/decoderX. 196 What: /sys/bus/cxl/devices/decoderX.Y
231 Date: June, 2021 197 Date: June, 2021
232 KernelVersion: v5.14 198 KernelVersion: v5.14
233 Contact: linux-cxl@vger.kernel.org 199 Contact: linux-cxl@vger.kernel.org
234 Description: 200 Description:
235 (RO) CXL decoder objects are e 201 (RO) CXL decoder objects are enumerated from either a platform
236 firmware description, or a CXL 202 firmware description, or a CXL HDM decoder register set in a
237 PCIe device (see CXL 2.0 secti 203 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
238 Capability Structure). The 'X' 204 Capability Structure). The 'X' in decoderX.Y represents the
239 cxl_port container of this dec 205 cxl_port container of this decoder, and 'Y' represents the
240 instance id of a given decoder 206 instance id of a given decoder resource.
241 207
242 208
243 What: /sys/bus/cxl/devices/decoderX. 209 What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
244 Date: June, 2021 210 Date: June, 2021
245 KernelVersion: v5.14 211 KernelVersion: v5.14
246 Contact: linux-cxl@vger.kernel.org 212 Contact: linux-cxl@vger.kernel.org
247 Description: 213 Description:
248 (RO) The 'start' and 'size' at 214 (RO) The 'start' and 'size' attributes together convey the
249 physical address base and numb 215 physical address base and number of bytes mapped in the
250 decoder's decode window. For d 216 decoder's decode window. For decoders of devtype
251 "cxl_decoder_root" the address 217 "cxl_decoder_root" the address range is fixed. For decoders of
252 devtype "cxl_decoder_switch" t 218 devtype "cxl_decoder_switch" the address is bounded by the
253 decode range of the cxl_port a 219 decode range of the cxl_port ancestor of the decoder's cxl_port,
254 and dynamically updates based 220 and dynamically updates based on the active memory regions in
255 that address space. 221 that address space.
256 222
257 223
258 What: /sys/bus/cxl/devices/decoderX. 224 What: /sys/bus/cxl/devices/decoderX.Y/locked
259 Date: June, 2021 225 Date: June, 2021
260 KernelVersion: v5.14 226 KernelVersion: v5.14
261 Contact: linux-cxl@vger.kernel.org 227 Contact: linux-cxl@vger.kernel.org
262 Description: 228 Description:
263 (RO) CXL HDM decoders have the 229 (RO) CXL HDM decoders have the capability to lock the
264 configuration until the next d 230 configuration until the next device reset. For decoders of
265 devtype "cxl_decoder_root" the 231 devtype "cxl_decoder_root" there is no standard facility to
266 unlock them. For decoders of 232 unlock them. For decoders of devtype "cxl_decoder_switch" a
267 secondary bus reset, of the PC 233 secondary bus reset, of the PCIe bridge that provides the bus
268 for this decoders uport, unloc 234 for this decoders uport, unlocks / resets the decoder.
269 235
270 236
271 What: /sys/bus/cxl/devices/decoderX. 237 What: /sys/bus/cxl/devices/decoderX.Y/target_list
272 Date: June, 2021 238 Date: June, 2021
273 KernelVersion: v5.14 239 KernelVersion: v5.14
274 Contact: linux-cxl@vger.kernel.org 240 Contact: linux-cxl@vger.kernel.org
275 Description: 241 Description:
276 (RO) Display a comma separated 242 (RO) Display a comma separated list of the current decoder
277 target configuration. The list 243 target configuration. The list is ordered by the current
278 configured interleave order of 244 configured interleave order of the decoder's dport instances.
279 Each entry in the list is a dp 245 Each entry in the list is a dport id.
280 246
281 247
282 What: /sys/bus/cxl/devices/decoderX. 248 What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
283 Date: June, 2021 249 Date: June, 2021
284 KernelVersion: v5.14 250 KernelVersion: v5.14
285 Contact: linux-cxl@vger.kernel.org 251 Contact: linux-cxl@vger.kernel.org
286 Description: 252 Description:
287 (RO) When a CXL decoder is of 253 (RO) When a CXL decoder is of devtype "cxl_decoder_root", it
288 represents a fixed memory wind 254 represents a fixed memory window identified by platform
289 firmware. A fixed window may o 255 firmware. A fixed window may only support a subset of memory
290 types. The 'cap_*' attributes 256 types. The 'cap_*' attributes indicate whether persistent
291 memory, volatile memory, accel 257 memory, volatile memory, accelerator memory, and / or expander
292 memory may be mapped behind th 258 memory may be mapped behind this decoder's memory window.
293 259
294 260
295 What: /sys/bus/cxl/devices/decoderX. 261 What: /sys/bus/cxl/devices/decoderX.Y/target_type
296 Date: June, 2021 262 Date: June, 2021
297 KernelVersion: v5.14 263 KernelVersion: v5.14
298 Contact: linux-cxl@vger.kernel.org 264 Contact: linux-cxl@vger.kernel.org
299 Description: 265 Description:
300 (RO) When a CXL decoder is of 266 (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it
301 can optionally decode either a 267 can optionally decode either accelerator memory (type-2) or
302 expander memory (type-3). The 268 expander memory (type-3). The 'target_type' attribute indicates
303 the current setting which may 269 the current setting which may dynamically change based on what
304 memory regions are activated i 270 memory regions are activated in this decode hierarchy.
305 271
306 272
307 What: /sys/bus/cxl/devices/endpointX 273 What: /sys/bus/cxl/devices/endpointX/CDAT
308 Date: July, 2022 274 Date: July, 2022
309 KernelVersion: v6.0 275 KernelVersion: v6.0
310 Contact: linux-cxl@vger.kernel.org 276 Contact: linux-cxl@vger.kernel.org
311 Description: 277 Description:
312 (RO) If this sysfs entry is no 278 (RO) If this sysfs entry is not present no DOE mailbox was
313 found to support CDAT data. I 279 found to support CDAT data. If it is present and the length of
314 the data is 0 reading the CDAT 280 the data is 0 reading the CDAT data failed. Otherwise the CDAT
315 data is reported. 281 data is reported.
316 282
317 283
318 What: /sys/bus/cxl/devices/decoderX. 284 What: /sys/bus/cxl/devices/decoderX.Y/mode
319 Date: May, 2022 285 Date: May, 2022
320 KernelVersion: v6.0 286 KernelVersion: v6.0
321 Contact: linux-cxl@vger.kernel.org 287 Contact: linux-cxl@vger.kernel.org
322 Description: 288 Description:
323 (RW) When a CXL decoder is of 289 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
324 translates from a host physica 290 translates from a host physical address range, to a device local
325 address range. Device-local ad 291 address range. Device-local address ranges are further split
326 into a 'ram' (volatile memory) 292 into a 'ram' (volatile memory) range and 'pmem' (persistent
327 memory) range. The 'mode' attr 293 memory) range. The 'mode' attribute emits one of 'ram', 'pmem',
328 'mixed', or 'none'. The 'mixed 294 'mixed', or 'none'. The 'mixed' indication is for error cases
329 when a decoder straddles the v 295 when a decoder straddles the volatile/persistent partition
330 boundary, and 'none' indicates 296 boundary, and 'none' indicates the decoder is not actively
331 decoding, or no DPA allocation 297 decoding, or no DPA allocation policy has been set.
332 298
333 'mode' can be written, when th 299 'mode' can be written, when the decoder is in the 'disabled'
334 state, with either 'ram' or 'p 300 state, with either 'ram' or 'pmem' to set the boundaries for the
335 next allocation. 301 next allocation.
336 302
337 303
338 What: /sys/bus/cxl/devices/decoderX. 304 What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource
339 Date: May, 2022 305 Date: May, 2022
340 KernelVersion: v6.0 306 KernelVersion: v6.0
341 Contact: linux-cxl@vger.kernel.org 307 Contact: linux-cxl@vger.kernel.org
342 Description: 308 Description:
343 (RO) When a CXL decoder is of 309 (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",
344 and its 'dpa_size' attribute i 310 and its 'dpa_size' attribute is non-zero, this attribute
345 indicates the device physical 311 indicates the device physical address (DPA) base address of the
346 allocation. 312 allocation.
347 313
348 314
349 What: /sys/bus/cxl/devices/decoderX. 315 What: /sys/bus/cxl/devices/decoderX.Y/dpa_size
350 Date: May, 2022 316 Date: May, 2022
351 KernelVersion: v6.0 317 KernelVersion: v6.0
352 Contact: linux-cxl@vger.kernel.org 318 Contact: linux-cxl@vger.kernel.org
353 Description: 319 Description:
354 (RW) When a CXL decoder is of 320 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
355 translates from a host physica 321 translates from a host physical address range, to a device local
356 address range. The range, base 322 address range. The range, base address plus length in bytes, of
357 DPA allocated to this decoder 323 DPA allocated to this decoder is conveyed in these 2 attributes.
358 Allocations can be mutated as 324 Allocations can be mutated as long as the decoder is in the
359 disabled state. A write to 'dp 325 disabled state. A write to 'dpa_size' releases the previous DPA
360 allocation and then attempts t 326 allocation and then attempts to allocate from the free capacity
361 in the device partition referr 327 in the device partition referred to by 'decoderX.Y/mode'.
362 Allocate and free requests can 328 Allocate and free requests can only be performed on the highest
363 instance number disabled decod 329 instance number disabled decoder with non-zero size. I.e.
364 allocations are enforced to oc 330 allocations are enforced to occur in increasing 'decoderX.Y/id'
365 order and frees are enforced t 331 order and frees are enforced to occur in decreasing
366 'decoderX.Y/id' order. 332 'decoderX.Y/id' order.
367 333
368 334
369 What: /sys/bus/cxl/devices/decoderX. 335 What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways
370 Date: May, 2022 336 Date: May, 2022
371 KernelVersion: v6.0 337 KernelVersion: v6.0
372 Contact: linux-cxl@vger.kernel.org 338 Contact: linux-cxl@vger.kernel.org
373 Description: 339 Description:
374 (RO) The number of targets acr 340 (RO) The number of targets across which this decoder's host
375 physical address (HPA) memory 341 physical address (HPA) memory range is interleaved. The device
376 maps every Nth block of HPA (o 342 maps every Nth block of HPA (of size ==
377 'interleave_granularity') to c 343 'interleave_granularity') to consecutive DPA addresses. The
378 decoder's position in the inte 344 decoder's position in the interleave is determined by the
379 device's (endpoint or switch) 345 device's (endpoint or switch) switch ancestry. For root
380 decoders their interleave is s 346 decoders their interleave is specified by platform firmware and
381 they only specify a downstream 347 they only specify a downstream target order for host bridges.
382 348
383 349
384 What: /sys/bus/cxl/devices/decoderX. 350 What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity
385 Date: May, 2022 351 Date: May, 2022
386 KernelVersion: v6.0 352 KernelVersion: v6.0
387 Contact: linux-cxl@vger.kernel.org 353 Contact: linux-cxl@vger.kernel.org
388 Description: 354 Description:
389 (RO) The number of consecutive 355 (RO) The number of consecutive bytes of host physical address
390 space this decoder claims at a 356 space this decoder claims at address N before the decode rotates
391 to the next target in the inte 357 to the next target in the interleave at address N +
392 interleave_granularity (assumi 358 interleave_granularity (assuming N is aligned to
393 interleave_granularity). 359 interleave_granularity).
394 360
395 361
396 What: /sys/bus/cxl/devices/decoderX. 362 What: /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region
397 Date: May, 2022, January, 2023 363 Date: May, 2022, January, 2023
398 KernelVersion: v6.0 (pmem), v6.3 (ram) 364 KernelVersion: v6.0 (pmem), v6.3 (ram)
399 Contact: linux-cxl@vger.kernel.org 365 Contact: linux-cxl@vger.kernel.org
400 Description: 366 Description:
401 (RW) Write a string in the for 367 (RW) Write a string in the form 'regionZ' to start the process
402 of defining a new persistent, 368 of defining a new persistent, or volatile memory region
403 (interleave-set) within the de 369 (interleave-set) within the decode range bounded by root decoder
404 'decoderX.Y'. The value writte 370 'decoderX.Y'. The value written must match the current value
405 returned from reading this att 371 returned from reading this attribute. An atomic compare exchange
406 operation is done on write to 372 operation is done on write to assign the requested id to a
407 region and allocate the region 373 region and allocate the region-id for the next creation attempt.
408 EBUSY is returned if the regio 374 EBUSY is returned if the region name written does not match the
409 current cached value. 375 current cached value.
410 376
411 377
412 What: /sys/bus/cxl/devices/decoderX. 378 What: /sys/bus/cxl/devices/decoderX.Y/delete_region
413 Date: May, 2022 379 Date: May, 2022
414 KernelVersion: v6.0 380 KernelVersion: v6.0
415 Contact: linux-cxl@vger.kernel.org 381 Contact: linux-cxl@vger.kernel.org
416 Description: 382 Description:
417 (WO) Write a string in the for 383 (WO) Write a string in the form 'regionZ' to delete that region,
418 provided it is currently idle 384 provided it is currently idle / not bound to a driver.
419 385
420 386
421 What: /sys/bus/cxl/devices/decoderX. 387 What: /sys/bus/cxl/devices/decoderX.Y/qos_class
422 Date: May, 2023 388 Date: May, 2023
423 KernelVersion: v6.5 389 KernelVersion: v6.5
424 Contact: linux-cxl@vger.kernel.org 390 Contact: linux-cxl@vger.kernel.org
425 Description: 391 Description:
426 (RO) For CXL host platforms th 392 (RO) For CXL host platforms that support "QoS Telemmetry" this
427 root-decoder-only attribute co 393 root-decoder-only attribute conveys a platform specific cookie
428 that identifies a QoS performa 394 that identifies a QoS performance class for the CXL Window.
429 This class-id can be compared 395 This class-id can be compared against a similar "qos_class"
430 published for each memory-type 396 published for each memory-type that an endpoint supports. While
431 it is not required that endpoi 397 it is not required that endpoints map their local memory-class
432 to a matching platform class, 398 to a matching platform class, mismatches are not recommended and
433 there are platform specific si 399 there are platform specific side-effects that may result.
434 400
435 401
436 What: /sys/bus/cxl/devices/regionZ/u 402 What: /sys/bus/cxl/devices/regionZ/uuid
437 Date: May, 2022 403 Date: May, 2022
438 KernelVersion: v6.0 404 KernelVersion: v6.0
439 Contact: linux-cxl@vger.kernel.org 405 Contact: linux-cxl@vger.kernel.org
440 Description: 406 Description:
441 (RW) Write a unique identifier 407 (RW) Write a unique identifier for the region. This field must
442 be set for persistent regions 408 be set for persistent regions and it must not conflict with the
443 UUID of another region. For vo 409 UUID of another region. For volatile ram regions this
444 attribute is a read-only empty 410 attribute is a read-only empty string.
445 411
446 412
447 What: /sys/bus/cxl/devices/regionZ/i 413 What: /sys/bus/cxl/devices/regionZ/interleave_granularity
448 Date: May, 2022 414 Date: May, 2022
449 KernelVersion: v6.0 415 KernelVersion: v6.0
450 Contact: linux-cxl@vger.kernel.org 416 Contact: linux-cxl@vger.kernel.org
451 Description: 417 Description:
452 (RW) Set the number of consecu 418 (RW) Set the number of consecutive bytes each device in the
453 interleave set will claim. The 419 interleave set will claim. The possible interleave granularity
454 values are determined by the C 420 values are determined by the CXL spec and the participating
455 devices. 421 devices.
456 422
457 423
458 What: /sys/bus/cxl/devices/regionZ/i 424 What: /sys/bus/cxl/devices/regionZ/interleave_ways
459 Date: May, 2022 425 Date: May, 2022
460 KernelVersion: v6.0 426 KernelVersion: v6.0
461 Contact: linux-cxl@vger.kernel.org 427 Contact: linux-cxl@vger.kernel.org
462 Description: 428 Description:
463 (RW) Configures the number of 429 (RW) Configures the number of devices participating in the
464 region is set by writing this 430 region is set by writing this value. Each device will provide
465 1/interleave_ways of storage f 431 1/interleave_ways of storage for the region.
466 432
467 433
468 What: /sys/bus/cxl/devices/regionZ/s 434 What: /sys/bus/cxl/devices/regionZ/size
469 Date: May, 2022 435 Date: May, 2022
470 KernelVersion: v6.0 436 KernelVersion: v6.0
471 Contact: linux-cxl@vger.kernel.org 437 Contact: linux-cxl@vger.kernel.org
472 Description: 438 Description:
473 (RW) System physical address s 439 (RW) System physical address space to be consumed by the region.
474 When written trigger the drive 440 When written trigger the driver to allocate space out of the
475 parent root decoder's address 441 parent root decoder's address space. When read the size of the
476 address space is reported and 442 address space is reported and should match the span of the
477 region's resource attribute. S 443 region's resource attribute. Size shall be set after the
478 interleave configuration param 444 interleave configuration parameters. Once set it cannot be
479 changed, only freed by writing 445 changed, only freed by writing 0. The kernel makes no guarantees
480 that data is maintained over a 446 that data is maintained over an address space freeing event, and
481 there is no guarantee that a f 447 there is no guarantee that a free followed by an allocate
482 results in the same address be 448 results in the same address being allocated.
483 449
484 450
485 What: /sys/bus/cxl/devices/regionZ/m 451 What: /sys/bus/cxl/devices/regionZ/mode
486 Date: January, 2023 452 Date: January, 2023
487 KernelVersion: v6.3 453 KernelVersion: v6.3
488 Contact: linux-cxl@vger.kernel.org 454 Contact: linux-cxl@vger.kernel.org
489 Description: 455 Description:
490 (RO) The mode of a region is e 456 (RO) The mode of a region is established at region creation time
491 and dictates the mode of the e 457 and dictates the mode of the endpoint decoder that comprise the
492 region. For more details on th 458 region. For more details on the possible modes see
493 /sys/bus/cxl/devices/decoderX. 459 /sys/bus/cxl/devices/decoderX.Y/mode
494 460
495 461
496 What: /sys/bus/cxl/devices/regionZ/r 462 What: /sys/bus/cxl/devices/regionZ/resource
497 Date: May, 2022 463 Date: May, 2022
498 KernelVersion: v6.0 464 KernelVersion: v6.0
499 Contact: linux-cxl@vger.kernel.org 465 Contact: linux-cxl@vger.kernel.org
500 Description: 466 Description:
501 (RO) A region is a contiguous 467 (RO) A region is a contiguous partition of a CXL root decoder
502 address space. Region capacity 468 address space. Region capacity is allocated by writing to the
503 size attribute, the resulting 469 size attribute, the resulting physical address space determined
504 by the driver is reflected her 470 by the driver is reflected here. It is therefore not useful to
505 read this before writing a val 471 read this before writing a value to the size attribute.
506 472
507 473
508 What: /sys/bus/cxl/devices/regionZ/t 474 What: /sys/bus/cxl/devices/regionZ/target[0..N]
509 Date: May, 2022 475 Date: May, 2022
510 KernelVersion: v6.0 476 KernelVersion: v6.0
511 Contact: linux-cxl@vger.kernel.org 477 Contact: linux-cxl@vger.kernel.org
512 Description: 478 Description:
513 (RW) Write an endpoint decoder 479 (RW) Write an endpoint decoder object name to 'targetX' where X
514 is the intended position of th 480 is the intended position of the endpoint device in the region
515 interleave and N is the 'inter 481 interleave and N is the 'interleave_ways' setting for the
516 region. ENXIO is returned if t 482 region. ENXIO is returned if the write results in an impossible
517 to map decode scenario, like t 483 to map decode scenario, like the endpoint is unreachable at that
518 position relative to the root 484 position relative to the root decoder interleave. EBUSY is
519 returned if the position in th 485 returned if the position in the region is already occupied, or
520 if the region is not in a stat 486 if the region is not in a state to accept interleave
521 configuration changes. EINVAL 487 configuration changes. EINVAL is returned if the object name is
522 not an endpoint decoder. Once 488 not an endpoint decoder. Once all positions have been
523 successfully written a final v 489 successfully written a final validation for decode conflicts is
524 performed before activating th 490 performed before activating the region.
525 491
526 492
527 What: /sys/bus/cxl/devices/regionZ/c 493 What: /sys/bus/cxl/devices/regionZ/commit
528 Date: May, 2022 494 Date: May, 2022
529 KernelVersion: v6.0 495 KernelVersion: v6.0
530 Contact: linux-cxl@vger.kernel.org 496 Contact: linux-cxl@vger.kernel.org
531 Description: 497 Description:
532 (RW) Write a boolean 'true' st 498 (RW) Write a boolean 'true' string value to this attribute to
533 trigger the region to transiti 499 trigger the region to transition from the software programmed
534 state to the actively decoding 500 state to the actively decoding in hardware state. The commit
535 operation in addition to valid 501 operation in addition to validating that the region is in proper
536 configured state, validates th 502 configured state, validates that the decoders are being
537 committed in spec mandated ord 503 committed in spec mandated order (last committed decoder id +
538 1), and checks that the hardwa 504 1), and checks that the hardware accepts the commit request.
539 Reading this value indicates w 505 Reading this value indicates whether the region is committed or
540 not. 506 not.
541 507
542 508
543 What: /sys/bus/cxl/devices/memX/trig 509 What: /sys/bus/cxl/devices/memX/trigger_poison_list
544 Date: April, 2023 510 Date: April, 2023
545 KernelVersion: v6.4 511 KernelVersion: v6.4
546 Contact: linux-cxl@vger.kernel.org 512 Contact: linux-cxl@vger.kernel.org
547 Description: 513 Description:
548 (WO) When a boolean 'true' is 514 (WO) When a boolean 'true' is written to this attribute the
549 memdev driver retrieves the po 515 memdev driver retrieves the poison list from the device. The
550 list consists of addresses tha 516 list consists of addresses that are poisoned, or would result
551 in poison if accessed, and the 517 in poison if accessed, and the source of the poison. This
552 attribute is only visible for 518 attribute is only visible for devices supporting the
553 capability. The retrieved erro 519 capability. The retrieved errors are logged as kernel
554 events when cxl_poison event t 520 events when cxl_poison event tracing is enabled.
555 <<
556 <<
557 What: /sys/bus/cxl/devices/regionZ/a <<
558 /sys/bus/cxl/devices/regionZ/a <<
559 Date: Jan, 2024 <<
560 KernelVersion: v6.9 <<
561 Contact: linux-cxl@vger.kernel.org <<
562 Description: <<
563 (RO) The aggregated read or wr <<
564 number is the accumulated read <<
565 devices that contributes to th <<
566 identical data that should app <<
567 /sys/devices/system/node/nodeX <<
568 /sys/devices/system/node/nodeX <<
569 See Documentation/ABI/stable/s <<
570 the number to the closest init <<
571 number to the closest CPU. <<
572 <<
573 <<
574 What: /sys/bus/cxl/devices/regionZ/a <<
575 /sys/bus/cxl/devices/regionZ/a <<
576 Date: Jan, 2024 <<
577 KernelVersion: v6.9 <<
578 Contact: linux-cxl@vger.kernel.org <<
579 Description: <<
580 (RO) The read or write latency <<
581 the worst read or write latenc <<
582 contributes to the region in n <<
583 that should appear in <<
584 /sys/devices/system/node/nodeX <<
585 /sys/devices/system/node/nodeX <<
586 See Documentation/ABI/stable/s <<
587 the number to the closest init <<
588 number to the closest CPU. <<
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