1 What: /sys/bus/cxl/flush 1 What: /sys/bus/cxl/flush
2 Date: Januarry, 2022 2 Date: Januarry, 2022
3 KernelVersion: v5.18 3 KernelVersion: v5.18
4 Contact: linux-cxl@vger.kernel.org 4 Contact: linux-cxl@vger.kernel.org
5 Description: 5 Description:
6 (WO) If userspace manually unb 6 (WO) If userspace manually unbinds a port the kernel schedules
7 all descendant memdevs for unb 7 all descendant memdevs for unbind. Writing '1' to this attribute
8 flushes that work. 8 flushes that work.
9 9
10 <<
11 What: /sys/bus/cxl/devices/memX/firm 10 What: /sys/bus/cxl/devices/memX/firmware_version
12 Date: December, 2020 11 Date: December, 2020
13 KernelVersion: v5.12 12 KernelVersion: v5.12
14 Contact: linux-cxl@vger.kernel.org 13 Contact: linux-cxl@vger.kernel.org
15 Description: 14 Description:
16 (RO) "FW Revision" string as r 15 (RO) "FW Revision" string as reported by the Identify
17 Memory Device Output Payload i 16 Memory Device Output Payload in the CXL-2.0
18 specification. 17 specification.
19 18
20 <<
21 What: /sys/bus/cxl/devices/memX/ram/ 19 What: /sys/bus/cxl/devices/memX/ram/size
22 Date: December, 2020 20 Date: December, 2020
23 KernelVersion: v5.12 21 KernelVersion: v5.12
24 Contact: linux-cxl@vger.kernel.org 22 Contact: linux-cxl@vger.kernel.org
25 Description: 23 Description:
26 (RO) "Volatile Only Capacity" 24 (RO) "Volatile Only Capacity" as bytes. Represents the
27 identically named field in the 25 identically named field in the Identify Memory Device Output
28 Payload in the CXL-2.0 specifi 26 Payload in the CXL-2.0 specification.
29 27
30 <<
31 What: /sys/bus/cxl/devices/memX/ram/ <<
32 Date: May, 2023 <<
33 KernelVersion: v6.8 <<
34 Contact: linux-cxl@vger.kernel.org <<
35 Description: <<
36 (RO) For CXL host platforms th <<
37 this attribute conveys a comma <<
38 specific cookies that identifi <<
39 for the volatile partition of <<
40 class-ids can be compared agai <<
41 published for a root decoder. <<
42 that the endpoints map their l <<
43 matching platform class, misma <<
44 and there are platform specifi <<
45 side-effects that may result. <<
46 <<
47 <<
48 What: /sys/bus/cxl/devices/memX/pmem 28 What: /sys/bus/cxl/devices/memX/pmem/size
49 Date: December, 2020 29 Date: December, 2020
50 KernelVersion: v5.12 30 KernelVersion: v5.12
51 Contact: linux-cxl@vger.kernel.org 31 Contact: linux-cxl@vger.kernel.org
52 Description: 32 Description:
53 (RO) "Persistent Only Capacity 33 (RO) "Persistent Only Capacity" as bytes. Represents the
54 identically named field in the 34 identically named field in the Identify Memory Device Output
55 Payload in the CXL-2.0 specifi 35 Payload in the CXL-2.0 specification.
56 36
57 <<
58 What: /sys/bus/cxl/devices/memX/pmem <<
59 Date: May, 2023 <<
60 KernelVersion: v6.8 <<
61 Contact: linux-cxl@vger.kernel.org <<
62 Description: <<
63 (RO) For CXL host platforms th <<
64 this attribute conveys a comma <<
65 specific cookies that identifi <<
66 for the persistent partition o <<
67 class-ids can be compared agai <<
68 published for a root decoder. <<
69 that the endpoints map their l <<
70 matching platform class, misma <<
71 and there are platform specifi <<
72 side-effects that may result. <<
73 <<
74 <<
75 What: /sys/bus/cxl/devices/memX/seri 37 What: /sys/bus/cxl/devices/memX/serial
76 Date: January, 2022 38 Date: January, 2022
77 KernelVersion: v5.18 39 KernelVersion: v5.18
78 Contact: linux-cxl@vger.kernel.org 40 Contact: linux-cxl@vger.kernel.org
79 Description: 41 Description:
80 (RO) 64-bit serial number per 42 (RO) 64-bit serial number per the PCIe Device Serial Number
81 capability. Mandatory for CXL 43 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
82 Memory Device PCIe Capabilitie 44 Memory Device PCIe Capabilities and Extended Capabilities.
83 45
84 <<
85 What: /sys/bus/cxl/devices/memX/numa 46 What: /sys/bus/cxl/devices/memX/numa_node
86 Date: January, 2022 47 Date: January, 2022
87 KernelVersion: v5.18 48 KernelVersion: v5.18
88 Contact: linux-cxl@vger.kernel.org 49 Contact: linux-cxl@vger.kernel.org
89 Description: 50 Description:
90 (RO) If NUMA is enabled and th 51 (RO) If NUMA is enabled and the platform has affinitized the
91 host PCI device for this memor 52 host PCI device for this memory device, emit the CPU node
92 affinity for this device. 53 affinity for this device.
93 54
94 <<
95 What: /sys/bus/cxl/devices/memX/secu <<
96 Date: June, 2023 <<
97 KernelVersion: v6.5 <<
98 Contact: linux-cxl@vger.kernel.org <<
99 Description: <<
100 (RO) Reading this file will di <<
101 that device. Such states can b <<
102 a sanitization is currently un <<
103 for persistent memory: 'locked <<
104 sysfs entry is select/poll cap <<
105 upon completion of a sanitize <<
106 <<
107 <<
108 What: /sys/bus/cxl/devices/memX/secu <<
109 Date: June, 2023 <<
110 KernelVersion: v6.5 <<
111 Contact: linux-cxl@vger.kernel.org <<
112 Description: <<
113 (WO) Write a boolean 'true' st <<
114 sanitize the device to securel <<
115 This is done by ensuring that <<
116 whether it resides in persiste <<
117 or the LSA, is made permanentl <<
118 is appropriate for the media t <<
119 the device to be disabled, tha <<
120 HPA ranges. This permits avoid <<
121 management, relying instead fo <<
122 transitions between software p <<
123 states. If this file is not pr <<
124 support for the operation. <<
125 <<
126 <<
127 What /sys/bus/cxl/devices/memX/secu <<
128 Date: June, 2023 <<
129 KernelVersion: v6.5 <<
130 Contact: linux-cxl@vger.kernel.org <<
131 Description: <<
132 (WO) Write a boolean 'true' st <<
133 secure erase user data by chan <<
134 all user data areas of the dev <<
135 the device to be disabled, tha <<
136 HPA ranges. This permits avoid <<
137 management, relying instead fo <<
138 transitions between software p <<
139 states. If this file is not pr <<
140 support for the operation. <<
141 <<
142 <<
143 What: /sys/bus/cxl/devices/memX/firm <<
144 Date: April, 2023 <<
145 KernelVersion: v6.5 <<
146 Contact: linux-cxl@vger.kernel.org <<
147 Description: <<
148 (RW) Firmware uploader mechani <<
149 this directory can be used to <<
150 firmware for CXL devices. The <<
151 documented in sysfs-class-firm <<
152 <<
153 <<
154 What: /sys/bus/cxl/devices/*/devtype 55 What: /sys/bus/cxl/devices/*/devtype
155 Date: June, 2021 56 Date: June, 2021
156 KernelVersion: v5.14 57 KernelVersion: v5.14
157 Contact: linux-cxl@vger.kernel.org 58 Contact: linux-cxl@vger.kernel.org
158 Description: 59 Description:
159 (RO) CXL device objects export !! 60 CXL device objects export the devtype attribute which mirrors
160 mirrors the same value communi !! 61 the same value communicated in the DEVTYPE environment variable
161 variable for uevents for devic !! 62 for uevents for devices on the "cxl" bus.
162 <<
163 63
164 What: /sys/bus/cxl/devices/*/modalia 64 What: /sys/bus/cxl/devices/*/modalias
165 Date: December, 2021 65 Date: December, 2021
166 KernelVersion: v5.18 66 KernelVersion: v5.18
167 Contact: linux-cxl@vger.kernel.org 67 Contact: linux-cxl@vger.kernel.org
168 Description: 68 Description:
169 (RO) CXL device objects export !! 69 CXL device objects export the modalias attribute which mirrors
170 mirrors the same value communi !! 70 the same value communicated in the MODALIAS environment variable
171 variable for uevents for devic !! 71 for uevents for devices on the "cxl" bus.
172 <<
173 72
174 What: /sys/bus/cxl/devices/portX/upo 73 What: /sys/bus/cxl/devices/portX/uport
175 Date: June, 2021 74 Date: June, 2021
176 KernelVersion: v5.14 75 KernelVersion: v5.14
177 Contact: linux-cxl@vger.kernel.org 76 Contact: linux-cxl@vger.kernel.org
178 Description: 77 Description:
179 (RO) CXL port objects are enum !! 78 CXL port objects are enumerated from either a platform firmware
180 firmware device (ACPI0017 and !! 79 device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
181 port with CXL component regist !! 80 CXL component registers. The 'uport' symlink connects the CXL
182 the CXL portX object to the de !! 81 portX object to the device that published the CXL port
183 capability. 82 capability.
184 83
185 <<
186 What: /sys/bus/cxl/devices/{port,end <<
187 Date: January, 2023 <<
188 KernelVersion: v6.3 <<
189 Contact: linux-cxl@vger.kernel.org <<
190 Description: <<
191 (RO) CXL port objects are inst <<
192 a CXL/PCIe switch, and for eac <<
193 corresponding memory device in <<
194 descendant CXL port (switch or <<
195 useful to know which 'dport' o <<
196 routes to this descendant. The <<
197 the device representing the do <<
198 routes to {port,endpoint}X. <<
199 <<
200 <<
201 What: /sys/bus/cxl/devices/portX/dpo 84 What: /sys/bus/cxl/devices/portX/dportY
202 Date: June, 2021 85 Date: June, 2021
203 KernelVersion: v5.14 86 KernelVersion: v5.14
204 Contact: linux-cxl@vger.kernel.org 87 Contact: linux-cxl@vger.kernel.org
205 Description: 88 Description:
206 (RO) CXL port objects are enum !! 89 CXL port objects are enumerated from either a platform firmware
207 firmware device (ACPI0017 and !! 90 device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
208 port with CXL component regist !! 91 CXL component registers. The 'dportY' symlink identifies one or
209 identifies one or more downstr !! 92 more downstream ports that the upstream port may target in its
210 may target in its decode of CX !! 93 decode of CXL memory resources. The 'Y' integer reflects the
211 integer reflects the hardware !! 94 hardware port unique-id used in the hardware decoder target
212 hardware decoder target list. !! 95 list.
213 <<
214 <<
215 What: /sys/bus/cxl/devices/portX/dec <<
216 Date: October, 2023 <<
217 KernelVersion: v6.7 <<
218 Contact: linux-cxl@vger.kernel.org <<
219 Description: <<
220 (RO) A memory device is consid <<
221 decoders are in the "committed <<
222 CXL HDM Decoder n Control Regi <<
223 operations like "sanitize" are <<
224 decoding a Host Physical Addre <<
225 may be elevated without any re <<
226 enumerated, as this may be due <<
227 platform firwmare or a previou <<
228 <<
229 96
230 What: /sys/bus/cxl/devices/decoderX. 97 What: /sys/bus/cxl/devices/decoderX.Y
231 Date: June, 2021 98 Date: June, 2021
232 KernelVersion: v5.14 99 KernelVersion: v5.14
233 Contact: linux-cxl@vger.kernel.org 100 Contact: linux-cxl@vger.kernel.org
234 Description: 101 Description:
235 (RO) CXL decoder objects are e !! 102 CXL decoder objects are enumerated from either a platform
236 firmware description, or a CXL 103 firmware description, or a CXL HDM decoder register set in a
237 PCIe device (see CXL 2.0 secti 104 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
238 Capability Structure). The 'X' 105 Capability Structure). The 'X' in decoderX.Y represents the
239 cxl_port container of this dec 106 cxl_port container of this decoder, and 'Y' represents the
240 instance id of a given decoder 107 instance id of a given decoder resource.
241 108
242 <<
243 What: /sys/bus/cxl/devices/decoderX. 109 What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
244 Date: June, 2021 110 Date: June, 2021
245 KernelVersion: v5.14 111 KernelVersion: v5.14
246 Contact: linux-cxl@vger.kernel.org 112 Contact: linux-cxl@vger.kernel.org
247 Description: 113 Description:
248 (RO) The 'start' and 'size' at !! 114 The 'start' and 'size' attributes together convey the physical
249 physical address base and numb !! 115 address base and number of bytes mapped in the decoder's decode
250 decoder's decode window. For d !! 116 window. For decoders of devtype "cxl_decoder_root" the address
251 "cxl_decoder_root" the address !! 117 range is fixed. For decoders of devtype "cxl_decoder_switch" the
252 devtype "cxl_decoder_switch" t !! 118 address is bounded by the decode range of the cxl_port ancestor
253 decode range of the cxl_port a !! 119 of the decoder's cxl_port, and dynamically updates based on the
254 and dynamically updates based !! 120 active memory regions in that address space.
255 that address space. <<
256 <<
257 121
258 What: /sys/bus/cxl/devices/decoderX. 122 What: /sys/bus/cxl/devices/decoderX.Y/locked
259 Date: June, 2021 123 Date: June, 2021
260 KernelVersion: v5.14 124 KernelVersion: v5.14
261 Contact: linux-cxl@vger.kernel.org 125 Contact: linux-cxl@vger.kernel.org
262 Description: 126 Description:
263 (RO) CXL HDM decoders have the !! 127 CXL HDM decoders have the capability to lock the configuration
264 configuration until the next d !! 128 until the next device reset. For decoders of devtype
265 devtype "cxl_decoder_root" the !! 129 "cxl_decoder_root" there is no standard facility to unlock them.
266 unlock them. For decoders of !! 130 For decoders of devtype "cxl_decoder_switch" a secondary bus
267 secondary bus reset, of the PC !! 131 reset, of the PCIe bridge that provides the bus for this
268 for this decoders uport, unloc !! 132 decoders uport, unlocks / resets the decoder.
269 <<
270 133
271 What: /sys/bus/cxl/devices/decoderX. 134 What: /sys/bus/cxl/devices/decoderX.Y/target_list
272 Date: June, 2021 135 Date: June, 2021
273 KernelVersion: v5.14 136 KernelVersion: v5.14
274 Contact: linux-cxl@vger.kernel.org 137 Contact: linux-cxl@vger.kernel.org
275 Description: 138 Description:
276 (RO) Display a comma separated !! 139 Display a comma separated list of the current decoder target
277 target configuration. The list !! 140 configuration. The list is ordered by the current configured
278 configured interleave order of !! 141 interleave order of the decoder's dport instances. Each entry in
279 Each entry in the list is a dp !! 142 the list is a dport id.
280 <<
281 143
282 What: /sys/bus/cxl/devices/decoderX. 144 What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
283 Date: June, 2021 145 Date: June, 2021
284 KernelVersion: v5.14 146 KernelVersion: v5.14
285 Contact: linux-cxl@vger.kernel.org 147 Contact: linux-cxl@vger.kernel.org
286 Description: 148 Description:
287 (RO) When a CXL decoder is of !! 149 When a CXL decoder is of devtype "cxl_decoder_root", it
288 represents a fixed memory wind 150 represents a fixed memory window identified by platform
289 firmware. A fixed window may o 151 firmware. A fixed window may only support a subset of memory
290 types. The 'cap_*' attributes 152 types. The 'cap_*' attributes indicate whether persistent
291 memory, volatile memory, accel 153 memory, volatile memory, accelerator memory, and / or expander
292 memory may be mapped behind th 154 memory may be mapped behind this decoder's memory window.
293 155
294 <<
295 What: /sys/bus/cxl/devices/decoderX. 156 What: /sys/bus/cxl/devices/decoderX.Y/target_type
296 Date: June, 2021 157 Date: June, 2021
297 KernelVersion: v5.14 158 KernelVersion: v5.14
298 Contact: linux-cxl@vger.kernel.org 159 Contact: linux-cxl@vger.kernel.org
299 Description: 160 Description:
300 (RO) When a CXL decoder is of !! 161 When a CXL decoder is of devtype "cxl_decoder_switch", it can
301 can optionally decode either a !! 162 optionally decode either accelerator memory (type-2) or expander
302 expander memory (type-3). The !! 163 memory (type-3). The 'target_type' attribute indicates the
303 the current setting which may !! 164 current setting which may dynamically change based on what
304 memory regions are activated i 165 memory regions are activated in this decode hierarchy.
305 <<
306 <<
307 What: /sys/bus/cxl/devices/endpointX <<
308 Date: July, 2022 <<
309 KernelVersion: v6.0 <<
310 Contact: linux-cxl@vger.kernel.org <<
311 Description: <<
312 (RO) If this sysfs entry is no <<
313 found to support CDAT data. I <<
314 the data is 0 reading the CDAT <<
315 data is reported. <<
316 <<
317 <<
318 What: /sys/bus/cxl/devices/decoderX. <<
319 Date: May, 2022 <<
320 KernelVersion: v6.0 <<
321 Contact: linux-cxl@vger.kernel.org <<
322 Description: <<
323 (RW) When a CXL decoder is of <<
324 translates from a host physica <<
325 address range. Device-local ad <<
326 into a 'ram' (volatile memory) <<
327 memory) range. The 'mode' attr <<
328 'mixed', or 'none'. The 'mixed <<
329 when a decoder straddles the v <<
330 boundary, and 'none' indicates <<
331 decoding, or no DPA allocation <<
332 <<
333 'mode' can be written, when th <<
334 state, with either 'ram' or 'p <<
335 next allocation. <<
336 <<
337 <<
338 What: /sys/bus/cxl/devices/decoderX. <<
339 Date: May, 2022 <<
340 KernelVersion: v6.0 <<
341 Contact: linux-cxl@vger.kernel.org <<
342 Description: <<
343 (RO) When a CXL decoder is of <<
344 and its 'dpa_size' attribute i <<
345 indicates the device physical <<
346 allocation. <<
347 <<
348 <<
349 What: /sys/bus/cxl/devices/decoderX. <<
350 Date: May, 2022 <<
351 KernelVersion: v6.0 <<
352 Contact: linux-cxl@vger.kernel.org <<
353 Description: <<
354 (RW) When a CXL decoder is of <<
355 translates from a host physica <<
356 address range. The range, base <<
357 DPA allocated to this decoder <<
358 Allocations can be mutated as <<
359 disabled state. A write to 'dp <<
360 allocation and then attempts t <<
361 in the device partition referr <<
362 Allocate and free requests can <<
363 instance number disabled decod <<
364 allocations are enforced to oc <<
365 order and frees are enforced t <<
366 'decoderX.Y/id' order. <<
367 <<
368 <<
369 What: /sys/bus/cxl/devices/decoderX. <<
370 Date: May, 2022 <<
371 KernelVersion: v6.0 <<
372 Contact: linux-cxl@vger.kernel.org <<
373 Description: <<
374 (RO) The number of targets acr <<
375 physical address (HPA) memory <<
376 maps every Nth block of HPA (o <<
377 'interleave_granularity') to c <<
378 decoder's position in the inte <<
379 device's (endpoint or switch) <<
380 decoders their interleave is s <<
381 they only specify a downstream <<
382 <<
383 <<
384 What: /sys/bus/cxl/devices/decoderX. <<
385 Date: May, 2022 <<
386 KernelVersion: v6.0 <<
387 Contact: linux-cxl@vger.kernel.org <<
388 Description: <<
389 (RO) The number of consecutive <<
390 space this decoder claims at a <<
391 to the next target in the inte <<
392 interleave_granularity (assumi <<
393 interleave_granularity). <<
394 <<
395 <<
396 What: /sys/bus/cxl/devices/decoderX. <<
397 Date: May, 2022, January, 2023 <<
398 KernelVersion: v6.0 (pmem), v6.3 (ram) <<
399 Contact: linux-cxl@vger.kernel.org <<
400 Description: <<
401 (RW) Write a string in the for <<
402 of defining a new persistent, <<
403 (interleave-set) within the de <<
404 'decoderX.Y'. The value writte <<
405 returned from reading this att <<
406 operation is done on write to <<
407 region and allocate the region <<
408 EBUSY is returned if the regio <<
409 current cached value. <<
410 <<
411 <<
412 What: /sys/bus/cxl/devices/decoderX. <<
413 Date: May, 2022 <<
414 KernelVersion: v6.0 <<
415 Contact: linux-cxl@vger.kernel.org <<
416 Description: <<
417 (WO) Write a string in the for <<
418 provided it is currently idle <<
419 <<
420 <<
421 What: /sys/bus/cxl/devices/decoderX. <<
422 Date: May, 2023 <<
423 KernelVersion: v6.5 <<
424 Contact: linux-cxl@vger.kernel.org <<
425 Description: <<
426 (RO) For CXL host platforms th <<
427 root-decoder-only attribute co <<
428 that identifies a QoS performa <<
429 This class-id can be compared <<
430 published for each memory-type <<
431 it is not required that endpoi <<
432 to a matching platform class, <<
433 there are platform specific si <<
434 <<
435 <<
436 What: /sys/bus/cxl/devices/regionZ/u <<
437 Date: May, 2022 <<
438 KernelVersion: v6.0 <<
439 Contact: linux-cxl@vger.kernel.org <<
440 Description: <<
441 (RW) Write a unique identifier <<
442 be set for persistent regions <<
443 UUID of another region. For vo <<
444 attribute is a read-only empty <<
445 <<
446 <<
447 What: /sys/bus/cxl/devices/regionZ/i <<
448 Date: May, 2022 <<
449 KernelVersion: v6.0 <<
450 Contact: linux-cxl@vger.kernel.org <<
451 Description: <<
452 (RW) Set the number of consecu <<
453 interleave set will claim. The <<
454 values are determined by the C <<
455 devices. <<
456 <<
457 <<
458 What: /sys/bus/cxl/devices/regionZ/i <<
459 Date: May, 2022 <<
460 KernelVersion: v6.0 <<
461 Contact: linux-cxl@vger.kernel.org <<
462 Description: <<
463 (RW) Configures the number of <<
464 region is set by writing this <<
465 1/interleave_ways of storage f <<
466 <<
467 <<
468 What: /sys/bus/cxl/devices/regionZ/s <<
469 Date: May, 2022 <<
470 KernelVersion: v6.0 <<
471 Contact: linux-cxl@vger.kernel.org <<
472 Description: <<
473 (RW) System physical address s <<
474 When written trigger the drive <<
475 parent root decoder's address <<
476 address space is reported and <<
477 region's resource attribute. S <<
478 interleave configuration param <<
479 changed, only freed by writing <<
480 that data is maintained over a <<
481 there is no guarantee that a f <<
482 results in the same address be <<
483 <<
484 <<
485 What: /sys/bus/cxl/devices/regionZ/m <<
486 Date: January, 2023 <<
487 KernelVersion: v6.3 <<
488 Contact: linux-cxl@vger.kernel.org <<
489 Description: <<
490 (RO) The mode of a region is e <<
491 and dictates the mode of the e <<
492 region. For more details on th <<
493 /sys/bus/cxl/devices/decoderX. <<
494 <<
495 <<
496 What: /sys/bus/cxl/devices/regionZ/r <<
497 Date: May, 2022 <<
498 KernelVersion: v6.0 <<
499 Contact: linux-cxl@vger.kernel.org <<
500 Description: <<
501 (RO) A region is a contiguous <<
502 address space. Region capacity <<
503 size attribute, the resulting <<
504 by the driver is reflected her <<
505 read this before writing a val <<
506 <<
507 <<
508 What: /sys/bus/cxl/devices/regionZ/t <<
509 Date: May, 2022 <<
510 KernelVersion: v6.0 <<
511 Contact: linux-cxl@vger.kernel.org <<
512 Description: <<
513 (RW) Write an endpoint decoder <<
514 is the intended position of th <<
515 interleave and N is the 'inter <<
516 region. ENXIO is returned if t <<
517 to map decode scenario, like t <<
518 position relative to the root <<
519 returned if the position in th <<
520 if the region is not in a stat <<
521 configuration changes. EINVAL <<
522 not an endpoint decoder. Once <<
523 successfully written a final v <<
524 performed before activating th <<
525 <<
526 <<
527 What: /sys/bus/cxl/devices/regionZ/c <<
528 Date: May, 2022 <<
529 KernelVersion: v6.0 <<
530 Contact: linux-cxl@vger.kernel.org <<
531 Description: <<
532 (RW) Write a boolean 'true' st <<
533 trigger the region to transiti <<
534 state to the actively decoding <<
535 operation in addition to valid <<
536 configured state, validates th <<
537 committed in spec mandated ord <<
538 1), and checks that the hardwa <<
539 Reading this value indicates w <<
540 not. <<
541 <<
542 <<
543 What: /sys/bus/cxl/devices/memX/trig <<
544 Date: April, 2023 <<
545 KernelVersion: v6.4 <<
546 Contact: linux-cxl@vger.kernel.org <<
547 Description: <<
548 (WO) When a boolean 'true' is <<
549 memdev driver retrieves the po <<
550 list consists of addresses tha <<
551 in poison if accessed, and the <<
552 attribute is only visible for <<
553 capability. The retrieved erro <<
554 events when cxl_poison event t <<
555 <<
556 <<
557 What: /sys/bus/cxl/devices/regionZ/a <<
558 /sys/bus/cxl/devices/regionZ/a <<
559 Date: Jan, 2024 <<
560 KernelVersion: v6.9 <<
561 Contact: linux-cxl@vger.kernel.org <<
562 Description: <<
563 (RO) The aggregated read or wr <<
564 number is the accumulated read <<
565 devices that contributes to th <<
566 identical data that should app <<
567 /sys/devices/system/node/nodeX <<
568 /sys/devices/system/node/nodeX <<
569 See Documentation/ABI/stable/s <<
570 the number to the closest init <<
571 number to the closest CPU. <<
572 <<
573 <<
574 What: /sys/bus/cxl/devices/regionZ/a <<
575 /sys/bus/cxl/devices/regionZ/a <<
576 Date: Jan, 2024 <<
577 KernelVersion: v6.9 <<
578 Contact: linux-cxl@vger.kernel.org <<
579 Description: <<
580 (RO) The read or write latency <<
581 the worst read or write latenc <<
582 contributes to the region in n <<
583 that should appear in <<
584 /sys/devices/system/node/nodeX <<
585 /sys/devices/system/node/nodeX <<
586 See Documentation/ABI/stable/s <<
587 the number to the closest init <<
588 number to the closest CPU. <<
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