1 What: /sys/bus/cxl/flush 1 What: /sys/bus/cxl/flush
2 Date: Januarry, 2022 2 Date: Januarry, 2022
3 KernelVersion: v5.18 3 KernelVersion: v5.18
4 Contact: linux-cxl@vger.kernel.org 4 Contact: linux-cxl@vger.kernel.org
5 Description: 5 Description:
6 (WO) If userspace manually unb 6 (WO) If userspace manually unbinds a port the kernel schedules
7 all descendant memdevs for unb 7 all descendant memdevs for unbind. Writing '1' to this attribute
8 flushes that work. 8 flushes that work.
9 9
10 10
11 What: /sys/bus/cxl/devices/memX/firm 11 What: /sys/bus/cxl/devices/memX/firmware_version
12 Date: December, 2020 12 Date: December, 2020
13 KernelVersion: v5.12 13 KernelVersion: v5.12
14 Contact: linux-cxl@vger.kernel.org 14 Contact: linux-cxl@vger.kernel.org
15 Description: 15 Description:
16 (RO) "FW Revision" string as r 16 (RO) "FW Revision" string as reported by the Identify
17 Memory Device Output Payload i 17 Memory Device Output Payload in the CXL-2.0
18 specification. 18 specification.
19 19
20 20
21 What: /sys/bus/cxl/devices/memX/ram/ 21 What: /sys/bus/cxl/devices/memX/ram/size
22 Date: December, 2020 22 Date: December, 2020
23 KernelVersion: v5.12 23 KernelVersion: v5.12
24 Contact: linux-cxl@vger.kernel.org 24 Contact: linux-cxl@vger.kernel.org
25 Description: 25 Description:
26 (RO) "Volatile Only Capacity" 26 (RO) "Volatile Only Capacity" as bytes. Represents the
27 identically named field in the 27 identically named field in the Identify Memory Device Output
28 Payload in the CXL-2.0 specifi 28 Payload in the CXL-2.0 specification.
29 29
30 30
31 What: /sys/bus/cxl/devices/memX/ram/ <<
32 Date: May, 2023 <<
33 KernelVersion: v6.8 <<
34 Contact: linux-cxl@vger.kernel.org <<
35 Description: <<
36 (RO) For CXL host platforms th <<
37 this attribute conveys a comma <<
38 specific cookies that identifi <<
39 for the volatile partition of <<
40 class-ids can be compared agai <<
41 published for a root decoder. <<
42 that the endpoints map their l <<
43 matching platform class, misma <<
44 and there are platform specifi <<
45 side-effects that may result. <<
46 <<
47 <<
48 What: /sys/bus/cxl/devices/memX/pmem 31 What: /sys/bus/cxl/devices/memX/pmem/size
49 Date: December, 2020 32 Date: December, 2020
50 KernelVersion: v5.12 33 KernelVersion: v5.12
51 Contact: linux-cxl@vger.kernel.org 34 Contact: linux-cxl@vger.kernel.org
52 Description: 35 Description:
53 (RO) "Persistent Only Capacity 36 (RO) "Persistent Only Capacity" as bytes. Represents the
54 identically named field in the 37 identically named field in the Identify Memory Device Output
55 Payload in the CXL-2.0 specifi 38 Payload in the CXL-2.0 specification.
56 39
57 40
58 What: /sys/bus/cxl/devices/memX/pmem <<
59 Date: May, 2023 <<
60 KernelVersion: v6.8 <<
61 Contact: linux-cxl@vger.kernel.org <<
62 Description: <<
63 (RO) For CXL host platforms th <<
64 this attribute conveys a comma <<
65 specific cookies that identifi <<
66 for the persistent partition o <<
67 class-ids can be compared agai <<
68 published for a root decoder. <<
69 that the endpoints map their l <<
70 matching platform class, misma <<
71 and there are platform specifi <<
72 side-effects that may result. <<
73 <<
74 <<
75 What: /sys/bus/cxl/devices/memX/seri 41 What: /sys/bus/cxl/devices/memX/serial
76 Date: January, 2022 42 Date: January, 2022
77 KernelVersion: v5.18 43 KernelVersion: v5.18
78 Contact: linux-cxl@vger.kernel.org 44 Contact: linux-cxl@vger.kernel.org
79 Description: 45 Description:
80 (RO) 64-bit serial number per 46 (RO) 64-bit serial number per the PCIe Device Serial Number
81 capability. Mandatory for CXL 47 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
82 Memory Device PCIe Capabilitie 48 Memory Device PCIe Capabilities and Extended Capabilities.
83 49
84 50
85 What: /sys/bus/cxl/devices/memX/numa 51 What: /sys/bus/cxl/devices/memX/numa_node
86 Date: January, 2022 52 Date: January, 2022
87 KernelVersion: v5.18 53 KernelVersion: v5.18
88 Contact: linux-cxl@vger.kernel.org 54 Contact: linux-cxl@vger.kernel.org
89 Description: 55 Description:
90 (RO) If NUMA is enabled and th 56 (RO) If NUMA is enabled and the platform has affinitized the
91 host PCI device for this memor 57 host PCI device for this memory device, emit the CPU node
92 affinity for this device. 58 affinity for this device.
93 59
94 60
95 What: /sys/bus/cxl/devices/memX/secu <<
96 Date: June, 2023 <<
97 KernelVersion: v6.5 <<
98 Contact: linux-cxl@vger.kernel.org <<
99 Description: <<
100 (RO) Reading this file will di <<
101 that device. Such states can b <<
102 a sanitization is currently un <<
103 for persistent memory: 'locked <<
104 sysfs entry is select/poll cap <<
105 upon completion of a sanitize <<
106 <<
107 <<
108 What: /sys/bus/cxl/devices/memX/secu <<
109 Date: June, 2023 <<
110 KernelVersion: v6.5 <<
111 Contact: linux-cxl@vger.kernel.org <<
112 Description: <<
113 (WO) Write a boolean 'true' st <<
114 sanitize the device to securel <<
115 This is done by ensuring that <<
116 whether it resides in persiste <<
117 or the LSA, is made permanentl <<
118 is appropriate for the media t <<
119 the device to be disabled, tha <<
120 HPA ranges. This permits avoid <<
121 management, relying instead fo <<
122 transitions between software p <<
123 states. If this file is not pr <<
124 support for the operation. <<
125 <<
126 <<
127 What /sys/bus/cxl/devices/memX/secu <<
128 Date: June, 2023 <<
129 KernelVersion: v6.5 <<
130 Contact: linux-cxl@vger.kernel.org <<
131 Description: <<
132 (WO) Write a boolean 'true' st <<
133 secure erase user data by chan <<
134 all user data areas of the dev <<
135 the device to be disabled, tha <<
136 HPA ranges. This permits avoid <<
137 management, relying instead fo <<
138 transitions between software p <<
139 states. If this file is not pr <<
140 support for the operation. <<
141 <<
142 <<
143 What: /sys/bus/cxl/devices/memX/firm <<
144 Date: April, 2023 <<
145 KernelVersion: v6.5 <<
146 Contact: linux-cxl@vger.kernel.org <<
147 Description: <<
148 (RW) Firmware uploader mechani <<
149 this directory can be used to <<
150 firmware for CXL devices. The <<
151 documented in sysfs-class-firm <<
152 <<
153 <<
154 What: /sys/bus/cxl/devices/*/devtype 61 What: /sys/bus/cxl/devices/*/devtype
155 Date: June, 2021 62 Date: June, 2021
156 KernelVersion: v5.14 63 KernelVersion: v5.14
157 Contact: linux-cxl@vger.kernel.org 64 Contact: linux-cxl@vger.kernel.org
158 Description: 65 Description:
159 (RO) CXL device objects export 66 (RO) CXL device objects export the devtype attribute which
160 mirrors the same value communi 67 mirrors the same value communicated in the DEVTYPE environment
161 variable for uevents for devic 68 variable for uevents for devices on the "cxl" bus.
162 69
163 70
164 What: /sys/bus/cxl/devices/*/modalia 71 What: /sys/bus/cxl/devices/*/modalias
165 Date: December, 2021 72 Date: December, 2021
166 KernelVersion: v5.18 73 KernelVersion: v5.18
167 Contact: linux-cxl@vger.kernel.org 74 Contact: linux-cxl@vger.kernel.org
168 Description: 75 Description:
169 (RO) CXL device objects export 76 (RO) CXL device objects export the modalias attribute which
170 mirrors the same value communi 77 mirrors the same value communicated in the MODALIAS environment
171 variable for uevents for devic 78 variable for uevents for devices on the "cxl" bus.
172 79
173 80
174 What: /sys/bus/cxl/devices/portX/upo 81 What: /sys/bus/cxl/devices/portX/uport
175 Date: June, 2021 82 Date: June, 2021
176 KernelVersion: v5.14 83 KernelVersion: v5.14
177 Contact: linux-cxl@vger.kernel.org 84 Contact: linux-cxl@vger.kernel.org
178 Description: 85 Description:
179 (RO) CXL port objects are enum 86 (RO) CXL port objects are enumerated from either a platform
180 firmware device (ACPI0017 and 87 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
181 port with CXL component regist 88 port with CXL component registers. The 'uport' symlink connects
182 the CXL portX object to the de 89 the CXL portX object to the device that published the CXL port
183 capability. 90 capability.
184 91
185 92
186 What: /sys/bus/cxl/devices/{port,end <<
187 Date: January, 2023 <<
188 KernelVersion: v6.3 <<
189 Contact: linux-cxl@vger.kernel.org <<
190 Description: <<
191 (RO) CXL port objects are inst <<
192 a CXL/PCIe switch, and for eac <<
193 corresponding memory device in <<
194 descendant CXL port (switch or <<
195 useful to know which 'dport' o <<
196 routes to this descendant. The <<
197 the device representing the do <<
198 routes to {port,endpoint}X. <<
199 <<
200 <<
201 What: /sys/bus/cxl/devices/portX/dpo 93 What: /sys/bus/cxl/devices/portX/dportY
202 Date: June, 2021 94 Date: June, 2021
203 KernelVersion: v5.14 95 KernelVersion: v5.14
204 Contact: linux-cxl@vger.kernel.org 96 Contact: linux-cxl@vger.kernel.org
205 Description: 97 Description:
206 (RO) CXL port objects are enum 98 (RO) CXL port objects are enumerated from either a platform
207 firmware device (ACPI0017 and 99 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
208 port with CXL component regist 100 port with CXL component registers. The 'dportY' symlink
209 identifies one or more downstr 101 identifies one or more downstream ports that the upstream port
210 may target in its decode of CX 102 may target in its decode of CXL memory resources. The 'Y'
211 integer reflects the hardware 103 integer reflects the hardware port unique-id used in the
212 hardware decoder target list. 104 hardware decoder target list.
213 105
214 106
215 What: /sys/bus/cxl/devices/portX/dec <<
216 Date: October, 2023 <<
217 KernelVersion: v6.7 <<
218 Contact: linux-cxl@vger.kernel.org <<
219 Description: <<
220 (RO) A memory device is consid <<
221 decoders are in the "committed <<
222 CXL HDM Decoder n Control Regi <<
223 operations like "sanitize" are <<
224 decoding a Host Physical Addre <<
225 may be elevated without any re <<
226 enumerated, as this may be due <<
227 platform firwmare or a previou <<
228 <<
229 <<
230 What: /sys/bus/cxl/devices/decoderX. 107 What: /sys/bus/cxl/devices/decoderX.Y
231 Date: June, 2021 108 Date: June, 2021
232 KernelVersion: v5.14 109 KernelVersion: v5.14
233 Contact: linux-cxl@vger.kernel.org 110 Contact: linux-cxl@vger.kernel.org
234 Description: 111 Description:
235 (RO) CXL decoder objects are e 112 (RO) CXL decoder objects are enumerated from either a platform
236 firmware description, or a CXL 113 firmware description, or a CXL HDM decoder register set in a
237 PCIe device (see CXL 2.0 secti 114 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
238 Capability Structure). The 'X' 115 Capability Structure). The 'X' in decoderX.Y represents the
239 cxl_port container of this dec 116 cxl_port container of this decoder, and 'Y' represents the
240 instance id of a given decoder 117 instance id of a given decoder resource.
241 118
242 119
243 What: /sys/bus/cxl/devices/decoderX. 120 What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
244 Date: June, 2021 121 Date: June, 2021
245 KernelVersion: v5.14 122 KernelVersion: v5.14
246 Contact: linux-cxl@vger.kernel.org 123 Contact: linux-cxl@vger.kernel.org
247 Description: 124 Description:
248 (RO) The 'start' and 'size' at 125 (RO) The 'start' and 'size' attributes together convey the
249 physical address base and numb 126 physical address base and number of bytes mapped in the
250 decoder's decode window. For d 127 decoder's decode window. For decoders of devtype
251 "cxl_decoder_root" the address 128 "cxl_decoder_root" the address range is fixed. For decoders of
252 devtype "cxl_decoder_switch" t 129 devtype "cxl_decoder_switch" the address is bounded by the
253 decode range of the cxl_port a 130 decode range of the cxl_port ancestor of the decoder's cxl_port,
254 and dynamically updates based 131 and dynamically updates based on the active memory regions in
255 that address space. 132 that address space.
256 133
257 134
258 What: /sys/bus/cxl/devices/decoderX. 135 What: /sys/bus/cxl/devices/decoderX.Y/locked
259 Date: June, 2021 136 Date: June, 2021
260 KernelVersion: v5.14 137 KernelVersion: v5.14
261 Contact: linux-cxl@vger.kernel.org 138 Contact: linux-cxl@vger.kernel.org
262 Description: 139 Description:
263 (RO) CXL HDM decoders have the 140 (RO) CXL HDM decoders have the capability to lock the
264 configuration until the next d 141 configuration until the next device reset. For decoders of
265 devtype "cxl_decoder_root" the 142 devtype "cxl_decoder_root" there is no standard facility to
266 unlock them. For decoders of 143 unlock them. For decoders of devtype "cxl_decoder_switch" a
267 secondary bus reset, of the PC 144 secondary bus reset, of the PCIe bridge that provides the bus
268 for this decoders uport, unloc 145 for this decoders uport, unlocks / resets the decoder.
269 146
270 147
271 What: /sys/bus/cxl/devices/decoderX. 148 What: /sys/bus/cxl/devices/decoderX.Y/target_list
272 Date: June, 2021 149 Date: June, 2021
273 KernelVersion: v5.14 150 KernelVersion: v5.14
274 Contact: linux-cxl@vger.kernel.org 151 Contact: linux-cxl@vger.kernel.org
275 Description: 152 Description:
276 (RO) Display a comma separated 153 (RO) Display a comma separated list of the current decoder
277 target configuration. The list 154 target configuration. The list is ordered by the current
278 configured interleave order of 155 configured interleave order of the decoder's dport instances.
279 Each entry in the list is a dp 156 Each entry in the list is a dport id.
280 157
281 158
282 What: /sys/bus/cxl/devices/decoderX. 159 What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
283 Date: June, 2021 160 Date: June, 2021
284 KernelVersion: v5.14 161 KernelVersion: v5.14
285 Contact: linux-cxl@vger.kernel.org 162 Contact: linux-cxl@vger.kernel.org
286 Description: 163 Description:
287 (RO) When a CXL decoder is of 164 (RO) When a CXL decoder is of devtype "cxl_decoder_root", it
288 represents a fixed memory wind 165 represents a fixed memory window identified by platform
289 firmware. A fixed window may o 166 firmware. A fixed window may only support a subset of memory
290 types. The 'cap_*' attributes 167 types. The 'cap_*' attributes indicate whether persistent
291 memory, volatile memory, accel 168 memory, volatile memory, accelerator memory, and / or expander
292 memory may be mapped behind th 169 memory may be mapped behind this decoder's memory window.
293 170
294 171
295 What: /sys/bus/cxl/devices/decoderX. 172 What: /sys/bus/cxl/devices/decoderX.Y/target_type
296 Date: June, 2021 173 Date: June, 2021
297 KernelVersion: v5.14 174 KernelVersion: v5.14
298 Contact: linux-cxl@vger.kernel.org 175 Contact: linux-cxl@vger.kernel.org
299 Description: 176 Description:
300 (RO) When a CXL decoder is of 177 (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it
301 can optionally decode either a 178 can optionally decode either accelerator memory (type-2) or
302 expander memory (type-3). The 179 expander memory (type-3). The 'target_type' attribute indicates
303 the current setting which may 180 the current setting which may dynamically change based on what
304 memory regions are activated i 181 memory regions are activated in this decode hierarchy.
305 182
306 183
307 What: /sys/bus/cxl/devices/endpointX 184 What: /sys/bus/cxl/devices/endpointX/CDAT
308 Date: July, 2022 185 Date: July, 2022
309 KernelVersion: v6.0 !! 186 KernelVersion: v5.20
310 Contact: linux-cxl@vger.kernel.org 187 Contact: linux-cxl@vger.kernel.org
311 Description: 188 Description:
312 (RO) If this sysfs entry is no 189 (RO) If this sysfs entry is not present no DOE mailbox was
313 found to support CDAT data. I 190 found to support CDAT data. If it is present and the length of
314 the data is 0 reading the CDAT 191 the data is 0 reading the CDAT data failed. Otherwise the CDAT
315 data is reported. 192 data is reported.
316 193
317 194
318 What: /sys/bus/cxl/devices/decoderX. 195 What: /sys/bus/cxl/devices/decoderX.Y/mode
319 Date: May, 2022 196 Date: May, 2022
320 KernelVersion: v6.0 !! 197 KernelVersion: v5.20
321 Contact: linux-cxl@vger.kernel.org 198 Contact: linux-cxl@vger.kernel.org
322 Description: 199 Description:
323 (RW) When a CXL decoder is of 200 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
324 translates from a host physica 201 translates from a host physical address range, to a device local
325 address range. Device-local ad 202 address range. Device-local address ranges are further split
326 into a 'ram' (volatile memory) 203 into a 'ram' (volatile memory) range and 'pmem' (persistent
327 memory) range. The 'mode' attr 204 memory) range. The 'mode' attribute emits one of 'ram', 'pmem',
328 'mixed', or 'none'. The 'mixed 205 'mixed', or 'none'. The 'mixed' indication is for error cases
329 when a decoder straddles the v 206 when a decoder straddles the volatile/persistent partition
330 boundary, and 'none' indicates 207 boundary, and 'none' indicates the decoder is not actively
331 decoding, or no DPA allocation 208 decoding, or no DPA allocation policy has been set.
332 209
333 'mode' can be written, when th 210 'mode' can be written, when the decoder is in the 'disabled'
334 state, with either 'ram' or 'p 211 state, with either 'ram' or 'pmem' to set the boundaries for the
335 next allocation. 212 next allocation.
336 213
337 214
338 What: /sys/bus/cxl/devices/decoderX. 215 What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource
339 Date: May, 2022 216 Date: May, 2022
340 KernelVersion: v6.0 !! 217 KernelVersion: v5.20
341 Contact: linux-cxl@vger.kernel.org 218 Contact: linux-cxl@vger.kernel.org
342 Description: 219 Description:
343 (RO) When a CXL decoder is of 220 (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",
344 and its 'dpa_size' attribute i 221 and its 'dpa_size' attribute is non-zero, this attribute
345 indicates the device physical 222 indicates the device physical address (DPA) base address of the
346 allocation. 223 allocation.
347 224
348 225
349 What: /sys/bus/cxl/devices/decoderX. 226 What: /sys/bus/cxl/devices/decoderX.Y/dpa_size
350 Date: May, 2022 227 Date: May, 2022
351 KernelVersion: v6.0 !! 228 KernelVersion: v5.20
352 Contact: linux-cxl@vger.kernel.org 229 Contact: linux-cxl@vger.kernel.org
353 Description: 230 Description:
354 (RW) When a CXL decoder is of 231 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
355 translates from a host physica 232 translates from a host physical address range, to a device local
356 address range. The range, base 233 address range. The range, base address plus length in bytes, of
357 DPA allocated to this decoder 234 DPA allocated to this decoder is conveyed in these 2 attributes.
358 Allocations can be mutated as 235 Allocations can be mutated as long as the decoder is in the
359 disabled state. A write to 'dp 236 disabled state. A write to 'dpa_size' releases the previous DPA
360 allocation and then attempts t 237 allocation and then attempts to allocate from the free capacity
361 in the device partition referr 238 in the device partition referred to by 'decoderX.Y/mode'.
362 Allocate and free requests can 239 Allocate and free requests can only be performed on the highest
363 instance number disabled decod 240 instance number disabled decoder with non-zero size. I.e.
364 allocations are enforced to oc 241 allocations are enforced to occur in increasing 'decoderX.Y/id'
365 order and frees are enforced t 242 order and frees are enforced to occur in decreasing
366 'decoderX.Y/id' order. 243 'decoderX.Y/id' order.
367 244
368 245
369 What: /sys/bus/cxl/devices/decoderX. 246 What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways
370 Date: May, 2022 247 Date: May, 2022
371 KernelVersion: v6.0 !! 248 KernelVersion: v5.20
372 Contact: linux-cxl@vger.kernel.org 249 Contact: linux-cxl@vger.kernel.org
373 Description: 250 Description:
374 (RO) The number of targets acr 251 (RO) The number of targets across which this decoder's host
375 physical address (HPA) memory 252 physical address (HPA) memory range is interleaved. The device
376 maps every Nth block of HPA (o 253 maps every Nth block of HPA (of size ==
377 'interleave_granularity') to c 254 'interleave_granularity') to consecutive DPA addresses. The
378 decoder's position in the inte 255 decoder's position in the interleave is determined by the
379 device's (endpoint or switch) 256 device's (endpoint or switch) switch ancestry. For root
380 decoders their interleave is s 257 decoders their interleave is specified by platform firmware and
381 they only specify a downstream 258 they only specify a downstream target order for host bridges.
382 259
383 260
384 What: /sys/bus/cxl/devices/decoderX. 261 What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity
385 Date: May, 2022 262 Date: May, 2022
386 KernelVersion: v6.0 !! 263 KernelVersion: v5.20
387 Contact: linux-cxl@vger.kernel.org 264 Contact: linux-cxl@vger.kernel.org
388 Description: 265 Description:
389 (RO) The number of consecutive 266 (RO) The number of consecutive bytes of host physical address
390 space this decoder claims at a 267 space this decoder claims at address N before the decode rotates
391 to the next target in the inte 268 to the next target in the interleave at address N +
392 interleave_granularity (assumi 269 interleave_granularity (assuming N is aligned to
393 interleave_granularity). 270 interleave_granularity).
394 271
395 272
396 What: /sys/bus/cxl/devices/decoderX. !! 273 What: /sys/bus/cxl/devices/decoderX.Y/create_pmem_region
397 Date: May, 2022, January, 2023 !! 274 Date: May, 2022
398 KernelVersion: v6.0 (pmem), v6.3 (ram) !! 275 KernelVersion: v5.20
399 Contact: linux-cxl@vger.kernel.org 276 Contact: linux-cxl@vger.kernel.org
400 Description: 277 Description:
401 (RW) Write a string in the for 278 (RW) Write a string in the form 'regionZ' to start the process
402 of defining a new persistent, !! 279 of defining a new persistent memory region (interleave-set)
403 (interleave-set) within the de !! 280 within the decode range bounded by root decoder 'decoderX.Y'.
404 'decoderX.Y'. The value writte !! 281 The value written must match the current value returned from
405 returned from reading this att !! 282 reading this attribute. An atomic compare exchange operation is
406 operation is done on write to !! 283 done on write to assign the requested id to a region and
407 region and allocate the region !! 284 allocate the region-id for the next creation attempt. EBUSY is
408 EBUSY is returned if the regio !! 285 returned if the region name written does not match the current
409 current cached value. !! 286 cached value.
410 287
411 288
412 What: /sys/bus/cxl/devices/decoderX. 289 What: /sys/bus/cxl/devices/decoderX.Y/delete_region
413 Date: May, 2022 290 Date: May, 2022
414 KernelVersion: v6.0 !! 291 KernelVersion: v5.20
415 Contact: linux-cxl@vger.kernel.org 292 Contact: linux-cxl@vger.kernel.org
416 Description: 293 Description:
417 (WO) Write a string in the for 294 (WO) Write a string in the form 'regionZ' to delete that region,
418 provided it is currently idle 295 provided it is currently idle / not bound to a driver.
419 296
420 297
421 What: /sys/bus/cxl/devices/decoderX. <<
422 Date: May, 2023 <<
423 KernelVersion: v6.5 <<
424 Contact: linux-cxl@vger.kernel.org <<
425 Description: <<
426 (RO) For CXL host platforms th <<
427 root-decoder-only attribute co <<
428 that identifies a QoS performa <<
429 This class-id can be compared <<
430 published for each memory-type <<
431 it is not required that endpoi <<
432 to a matching platform class, <<
433 there are platform specific si <<
434 <<
435 <<
436 What: /sys/bus/cxl/devices/regionZ/u 298 What: /sys/bus/cxl/devices/regionZ/uuid
437 Date: May, 2022 299 Date: May, 2022
438 KernelVersion: v6.0 !! 300 KernelVersion: v5.20
439 Contact: linux-cxl@vger.kernel.org 301 Contact: linux-cxl@vger.kernel.org
440 Description: 302 Description:
441 (RW) Write a unique identifier 303 (RW) Write a unique identifier for the region. This field must
442 be set for persistent regions 304 be set for persistent regions and it must not conflict with the
443 UUID of another region. For vo !! 305 UUID of another region.
444 attribute is a read-only empty <<
445 306
446 307
447 What: /sys/bus/cxl/devices/regionZ/i 308 What: /sys/bus/cxl/devices/regionZ/interleave_granularity
448 Date: May, 2022 309 Date: May, 2022
449 KernelVersion: v6.0 !! 310 KernelVersion: v5.20
450 Contact: linux-cxl@vger.kernel.org 311 Contact: linux-cxl@vger.kernel.org
451 Description: 312 Description:
452 (RW) Set the number of consecu 313 (RW) Set the number of consecutive bytes each device in the
453 interleave set will claim. The 314 interleave set will claim. The possible interleave granularity
454 values are determined by the C 315 values are determined by the CXL spec and the participating
455 devices. 316 devices.
456 317
457 318
458 What: /sys/bus/cxl/devices/regionZ/i 319 What: /sys/bus/cxl/devices/regionZ/interleave_ways
459 Date: May, 2022 320 Date: May, 2022
460 KernelVersion: v6.0 !! 321 KernelVersion: v5.20
461 Contact: linux-cxl@vger.kernel.org 322 Contact: linux-cxl@vger.kernel.org
462 Description: 323 Description:
463 (RW) Configures the number of 324 (RW) Configures the number of devices participating in the
464 region is set by writing this 325 region is set by writing this value. Each device will provide
465 1/interleave_ways of storage f 326 1/interleave_ways of storage for the region.
466 327
467 328
468 What: /sys/bus/cxl/devices/regionZ/s 329 What: /sys/bus/cxl/devices/regionZ/size
469 Date: May, 2022 330 Date: May, 2022
470 KernelVersion: v6.0 !! 331 KernelVersion: v5.20
471 Contact: linux-cxl@vger.kernel.org 332 Contact: linux-cxl@vger.kernel.org
472 Description: 333 Description:
473 (RW) System physical address s 334 (RW) System physical address space to be consumed by the region.
474 When written trigger the drive 335 When written trigger the driver to allocate space out of the
475 parent root decoder's address 336 parent root decoder's address space. When read the size of the
476 address space is reported and 337 address space is reported and should match the span of the
477 region's resource attribute. S 338 region's resource attribute. Size shall be set after the
478 interleave configuration param 339 interleave configuration parameters. Once set it cannot be
479 changed, only freed by writing 340 changed, only freed by writing 0. The kernel makes no guarantees
480 that data is maintained over a 341 that data is maintained over an address space freeing event, and
481 there is no guarantee that a f 342 there is no guarantee that a free followed by an allocate
482 results in the same address be 343 results in the same address being allocated.
483 344
484 345
485 What: /sys/bus/cxl/devices/regionZ/m <<
486 Date: January, 2023 <<
487 KernelVersion: v6.3 <<
488 Contact: linux-cxl@vger.kernel.org <<
489 Description: <<
490 (RO) The mode of a region is e <<
491 and dictates the mode of the e <<
492 region. For more details on th <<
493 /sys/bus/cxl/devices/decoderX. <<
494 <<
495 <<
496 What: /sys/bus/cxl/devices/regionZ/r 346 What: /sys/bus/cxl/devices/regionZ/resource
497 Date: May, 2022 347 Date: May, 2022
498 KernelVersion: v6.0 !! 348 KernelVersion: v5.20
499 Contact: linux-cxl@vger.kernel.org 349 Contact: linux-cxl@vger.kernel.org
500 Description: 350 Description:
501 (RO) A region is a contiguous 351 (RO) A region is a contiguous partition of a CXL root decoder
502 address space. Region capacity 352 address space. Region capacity is allocated by writing to the
503 size attribute, the resulting 353 size attribute, the resulting physical address space determined
504 by the driver is reflected her 354 by the driver is reflected here. It is therefore not useful to
505 read this before writing a val 355 read this before writing a value to the size attribute.
506 356
507 357
508 What: /sys/bus/cxl/devices/regionZ/t 358 What: /sys/bus/cxl/devices/regionZ/target[0..N]
509 Date: May, 2022 359 Date: May, 2022
510 KernelVersion: v6.0 !! 360 KernelVersion: v5.20
511 Contact: linux-cxl@vger.kernel.org 361 Contact: linux-cxl@vger.kernel.org
512 Description: 362 Description:
513 (RW) Write an endpoint decoder 363 (RW) Write an endpoint decoder object name to 'targetX' where X
514 is the intended position of th 364 is the intended position of the endpoint device in the region
515 interleave and N is the 'inter 365 interleave and N is the 'interleave_ways' setting for the
516 region. ENXIO is returned if t 366 region. ENXIO is returned if the write results in an impossible
517 to map decode scenario, like t 367 to map decode scenario, like the endpoint is unreachable at that
518 position relative to the root 368 position relative to the root decoder interleave. EBUSY is
519 returned if the position in th 369 returned if the position in the region is already occupied, or
520 if the region is not in a stat 370 if the region is not in a state to accept interleave
521 configuration changes. EINVAL 371 configuration changes. EINVAL is returned if the object name is
522 not an endpoint decoder. Once 372 not an endpoint decoder. Once all positions have been
523 successfully written a final v 373 successfully written a final validation for decode conflicts is
524 performed before activating th 374 performed before activating the region.
525 375
526 376
527 What: /sys/bus/cxl/devices/regionZ/c 377 What: /sys/bus/cxl/devices/regionZ/commit
528 Date: May, 2022 378 Date: May, 2022
529 KernelVersion: v6.0 !! 379 KernelVersion: v5.20
530 Contact: linux-cxl@vger.kernel.org 380 Contact: linux-cxl@vger.kernel.org
531 Description: 381 Description:
532 (RW) Write a boolean 'true' st 382 (RW) Write a boolean 'true' string value to this attribute to
533 trigger the region to transiti 383 trigger the region to transition from the software programmed
534 state to the actively decoding 384 state to the actively decoding in hardware state. The commit
535 operation in addition to valid 385 operation in addition to validating that the region is in proper
536 configured state, validates th 386 configured state, validates that the decoders are being
537 committed in spec mandated ord 387 committed in spec mandated order (last committed decoder id +
538 1), and checks that the hardwa 388 1), and checks that the hardware accepts the commit request.
539 Reading this value indicates w 389 Reading this value indicates whether the region is committed or
540 not. 390 not.
541 <<
542 <<
543 What: /sys/bus/cxl/devices/memX/trig <<
544 Date: April, 2023 <<
545 KernelVersion: v6.4 <<
546 Contact: linux-cxl@vger.kernel.org <<
547 Description: <<
548 (WO) When a boolean 'true' is <<
549 memdev driver retrieves the po <<
550 list consists of addresses tha <<
551 in poison if accessed, and the <<
552 attribute is only visible for <<
553 capability. The retrieved erro <<
554 events when cxl_poison event t <<
555 <<
556 <<
557 What: /sys/bus/cxl/devices/regionZ/a <<
558 /sys/bus/cxl/devices/regionZ/a <<
559 Date: Jan, 2024 <<
560 KernelVersion: v6.9 <<
561 Contact: linux-cxl@vger.kernel.org <<
562 Description: <<
563 (RO) The aggregated read or wr <<
564 number is the accumulated read <<
565 devices that contributes to th <<
566 identical data that should app <<
567 /sys/devices/system/node/nodeX <<
568 /sys/devices/system/node/nodeX <<
569 See Documentation/ABI/stable/s <<
570 the number to the closest init <<
571 number to the closest CPU. <<
572 <<
573 <<
574 What: /sys/bus/cxl/devices/regionZ/a <<
575 /sys/bus/cxl/devices/regionZ/a <<
576 Date: Jan, 2024 <<
577 KernelVersion: v6.9 <<
578 Contact: linux-cxl@vger.kernel.org <<
579 Description: <<
580 (RO) The read or write latency <<
581 the worst read or write latenc <<
582 contributes to the region in n <<
583 that should appear in <<
584 /sys/devices/system/node/nodeX <<
585 /sys/devices/system/node/nodeX <<
586 See Documentation/ABI/stable/s <<
587 the number to the closest init <<
588 number to the closest CPU. <<
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