1 What: /sys/class/fpga_manager/<fpga> 1 What: /sys/class/fpga_manager/<fpga>/name 2 Date: August 2015 2 Date: August 2015 3 KernelVersion: 4.3 3 KernelVersion: 4.3 4 Contact: Alan Tull <atull@opensource.alt 4 Contact: Alan Tull <atull@opensource.altera.com> 5 Description: Name of low level fpga manager 5 Description: Name of low level fpga manager driver. 6 6 7 What: /sys/class/fpga_manager/<fpga> 7 What: /sys/class/fpga_manager/<fpga>/state 8 Date: August 2015 8 Date: August 2015 9 KernelVersion: 4.3 9 KernelVersion: 4.3 10 Contact: Alan Tull <atull@opensource.alt 10 Contact: Alan Tull <atull@opensource.altera.com> 11 Description: Read fpga manager state as a s 11 Description: Read fpga manager state as a string. 12 The intent is to provide enoug 12 The intent is to provide enough detail that if something goes 13 wrong during FPGA programming 13 wrong during FPGA programming (something that the driver can't 14 fix) then userspace can know, 14 fix) then userspace can know, i.e. if the firmware request 15 fails, that could be due to no 15 fails, that could be due to not being able to find the firmware 16 file. 16 file. 17 17 18 This is a superset of FPGA sta 18 This is a superset of FPGA states and fpga manager driver 19 states. The fpga manager driv 19 states. The fpga manager driver is walking through these steps 20 to get the FPGA into a known o 20 to get the FPGA into a known operating state. It's a sequence, 21 though some steps may get skip 21 though some steps may get skipped. Valid FPGA states will vary 22 by manufacturer; this is a sup 22 by manufacturer; this is a superset. 23 23 24 * unknown = can' 24 * unknown = can't determine state 25 * power off = FPGA 25 * power off = FPGA power is off 26 * power up = FPGA 26 * power up = FPGA reports power is up 27 * reset = FPGA 27 * reset = FPGA held in reset state 28 * firmware request = firm 28 * firmware request = firmware class request in progress 29 * firmware request error = fir 29 * firmware request error = firmware request failed 30 * write init = prep 30 * write init = preparing FPGA for programming 31 * write init error = Erro !! 31 * write init error = Error while preparing FPGA for >> 32 programming 32 * write = FPGA 33 * write = FPGA ready to receive image data 33 * write error = Erro 34 * write error = Error while programming 34 * write complete = Doin 35 * write complete = Doing post programming steps 35 * write complete error = Erro 36 * write complete error = Error while doing post programming 36 * operating = FPGA 37 * operating = FPGA is programmed and operating 37 38 38 What: /sys/class/fpga_manager/<fpga> 39 What: /sys/class/fpga_manager/<fpga>/status 39 Date: June 2018 40 Date: June 2018 40 KernelVersion: 4.19 41 KernelVersion: 4.19 41 Contact: Wu Hao <hao.wu@intel.com> 42 Contact: Wu Hao <hao.wu@intel.com> 42 Description: Read fpga manager status as a 43 Description: Read fpga manager status as a string. 43 If FPGA programming operation 44 If FPGA programming operation fails, it could be caused by crc 44 error or incompatible bitstrea 45 error or incompatible bitstream image. The intent of this 45 interface is to provide more d 46 interface is to provide more detailed information for FPGA 46 programming errors to userspac 47 programming errors to userspace. This is a list of strings for 47 the supported status. 48 the supported status. 48 49 49 * reconfig operation error !! 50 * reconfig operation error - invalid operations detected by 50 51 reconfiguration hardware. 51 52 e.g. start reconfiguration 52 53 with errors not cleared 53 * reconfig CRC error 54 * reconfig CRC error - CRC error detected by 54 55 reconfiguration hardware. 55 * reconfig incompatible image 56 * reconfig incompatible image - reconfiguration image is 56 57 incompatible with hardware 57 * reconfig IP protocol error 58 * reconfig IP protocol error - protocol errors detected by 58 59 reconfiguration hardware 59 * reconfig fifo overflow error 60 * reconfig fifo overflow error - FIFO overflow detected by 60 61 reconfiguration hardware
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