1 What: /sys/bus/.../drivers/intel-m10 1 What: /sys/bus/.../drivers/intel-m10-bmc/.../bmc_version
2 Date: June 2020 2 Date: June 2020
3 KernelVersion: 5.10 3 KernelVersion: 5.10
4 Contact: Xu Yilun <yilun.xu@intel.com> 4 Contact: Xu Yilun <yilun.xu@intel.com>
5 Description: Read only. Returns the hardwar 5 Description: Read only. Returns the hardware build version of Intel
6 MAX10 BMC chip. 6 MAX10 BMC chip.
7 Format: "0x%x". 7 Format: "0x%x".
8 8
9 What: /sys/bus/.../drivers/intel-m10 9 What: /sys/bus/.../drivers/intel-m10-bmc/.../bmcfw_version
10 Date: June 2020 10 Date: June 2020
11 KernelVersion: 5.10 11 KernelVersion: 5.10
12 Contact: Xu Yilun <yilun.xu@intel.com> 12 Contact: Xu Yilun <yilun.xu@intel.com>
13 Description: Read only. Returns the firmwar 13 Description: Read only. Returns the firmware version of Intel MAX10
14 BMC chip. 14 BMC chip.
15 Format: "0x%x". 15 Format: "0x%x".
16 16
17 What: /sys/bus/.../drivers/intel-m10 17 What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_address
18 Date: January 2021 18 Date: January 2021
19 KernelVersion: 5.12 19 KernelVersion: 5.12
20 Contact: Peter Colberg <peter.colberg@in 20 Contact: Peter Colberg <peter.colberg@intel.com>
21 Description: Read only. Returns the first M 21 Description: Read only. Returns the first MAC address in a block
22 of sequential MAC addresses as 22 of sequential MAC addresses assigned to the board
23 that is managed by the Intel M 23 that is managed by the Intel MAX10 BMC. It is stored in
24 FLASH storage and is mirrored 24 FLASH storage and is mirrored in the MAX10 BMC register
25 space. 25 space.
26 Format: "%02x:%02x:%02x:%02x:% 26 Format: "%02x:%02x:%02x:%02x:%02x:%02x".
27 27
28 What: /sys/bus/.../drivers/intel-m10 28 What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_count
29 Date: January 2021 29 Date: January 2021
30 KernelVersion: 5.12 30 KernelVersion: 5.12
31 Contact: Peter Colberg <peter.colberg@in 31 Contact: Peter Colberg <peter.colberg@intel.com>
32 Description: Read only. Returns the number 32 Description: Read only. Returns the number of sequential MAC
33 addresses assigned to the boar 33 addresses assigned to the board managed by the Intel
34 MAX10 BMC. This value is store 34 MAX10 BMC. This value is stored in FLASH and is mirrored
35 in the MAX10 BMC register spac 35 in the MAX10 BMC register space.
36 Format: "%u". 36 Format: "%u".
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