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Linux/Documentation/ABI/testing/sysfs-driver-zynqmp-fpga

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Diff markup

Differences between /Documentation/ABI/testing/sysfs-driver-zynqmp-fpga (Version linux-6.12-rc7) and /Documentation/ABI/testing/sysfs-driver-zynqmp-fpga (Version linux-6.7.12)


  1 What:           /sys/bus/platform/drivers/zynq      1 What:           /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
  2 Date:           February 2023                       2 Date:           February 2023
  3 KernelVersion:  6.4                                 3 KernelVersion:  6.4
  4 Contact:        Nava kishore Manne <nava.kishor      4 Contact:        Nava kishore Manne <nava.kishore.manne@amd.com>
  5 Description:    (RO) Read fpga status.              5 Description:    (RO) Read fpga status.
  6                 Read returns a hexadecimal val      6                 Read returns a hexadecimal value that tells the current status
  7                 of the FPGA device. Each bit p      7                 of the FPGA device. Each bit position in the status value is
  8                 described Below(see ug570 chap      8                 described Below(see ug570 chapter 9).
  9                 https://docs.xilinx.com/v/u/en      9                 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
 10                                                    10 
 11                 ======================  ======     11                 ======================  ==============================================
 12                 BIT(0)                  0: No      12                 BIT(0)                  0: No CRC error
 13                                         1: CRC     13                                         1: CRC error
 14                                                    14 
 15                 BIT(1)                  0: Dec     15                 BIT(1)                  0: Decryptor security not set
 16                                         1: Dec     16                                         1: Decryptor security set
 17                                                    17 
 18                 BIT(2)                  0: MMC     18                 BIT(2)                  0: MMCMs/PLLs are not locked
 19                                         1: MMC     19                                         1: MMCMs/PLLs are locked
 20                                                    20 
 21                 BIT(3)                  0: DCI     21                 BIT(3)                  0: DCI not matched
 22                                         1: DCI     22                                         1: DCI matched
 23                                                    23 
 24                 BIT(4)                  0: Sta     24                 BIT(4)                  0: Start-up sequence has not finished
 25                                         1: Sta     25                                         1: Start-up sequence has finished
 26                                                    26 
 27                 BIT(5)                  0: All     27                 BIT(5)                  0: All I/Os are placed in High-Z state
 28                                         1: All     28                                         1: All I/Os behave as configured
 29                                                    29 
 30                 BIT(6)                  0: Fli     30                 BIT(6)                  0: Flip-flops and block RAM are write disabled
 31                                         1: Fli     31                                         1: Flip-flops and block RAM are write enabled
 32                                                    32 
 33                 BIT(7)                  0: GHI     33                 BIT(7)                  0: GHIGH_B_STATUS asserted
 34                                         1: GHI     34                                         1: GHIGH_B_STATUS deasserted
 35                                                    35 
 36                 BIT(8) to BIT(10)       Status     36                 BIT(8) to BIT(10)       Status of the mode pins
 37                                                    37 
 38                 BIT(11)                 0: Ini     38                 BIT(11)                 0: Initialization has not finished
 39                                         1: Ini     39                                         1: Initialization finished
 40                                                    40 
 41                 BIT(12)                 Value      41                 BIT(12)                 Value on INIT_B_PIN pin
 42                                                    42 
 43                 BIT(13)                 0: Sig     43                 BIT(13)                 0: Signal not released
 44                                         1: Sig     44                                         1: Signal released
 45                                                    45 
 46                 BIT(14)                 Value      46                 BIT(14)                 Value on DONE_PIN pin.
 47                                                    47 
 48                 BIT(15)                 0: No      48                 BIT(15)                 0: No IDCODE_ERROR
 49                                         1: IDC     49                                         1: IDCODE_ERROR
 50                                                    50 
 51                 BIT(16)                 0: No      51                 BIT(16)                 0: No SECURITY_ERROR
 52                                         1: SEC     52                                         1: SECURITY_ERROR
 53                                                    53 
 54                 BIT(17)                 System     54                 BIT(17)                 System Monitor over-temperature if set
 55                                                    55 
 56                 BIT(18) to BIT(20)      Start-     56                 BIT(18) to BIT(20)      Start-up state machine (0 to 7)
 57                                         Phase      57                                         Phase 0 = 000
 58                                         Phase      58                                         Phase 1 = 001
 59                                         Phase      59                                         Phase 2 = 011
 60                                         Phase      60                                         Phase 3 = 010
 61                                         Phase      61                                         Phase 4 = 110
 62                                         Phase      62                                         Phase 5 = 111
 63                                         Phase      63                                         Phase 6 = 101
 64                                         Phase      64                                         Phase 7 = 100
 65                                                    65 
 66                 BIT(25) to BIT(26)      Indica     66                 BIT(25) to BIT(26)      Indicates the detected bus width
 67                                         00 = x     67                                         00 = x1
 68                                         01 = x     68                                         01 = x8
 69                                         10 = x     69                                         10 = x16
 70                                         11 = x     70                                         11 = x32
 71                 ======================  ======     71                 ======================  ==============================================
 72                                                    72 
 73                 The other bits are reserved.       73                 The other bits are reserved.
                                                      

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