1 .. SPDX-License-Identifier: GPL-2.0
2
3 ===============
4 Boot Interrupts
5 ===============
6
7 :Author: - Sean V Kelley <sean.v.kelley@linux.i
8
9 Overview
10 ========
11
12 On PCI Express, interrupts are represented wit
13 interrupt messages (Assert_INTx/Deassert_INTx)
14 given Core IO converts the legacy interrupt me
15 MSI interrupts. If the IO-APIC is disabled (v
16 IO-APIC table entries), the messages are route
17 in-band interrupt mechanism was traditionally
18 did not support the IO-APIC and for boot. Inte
19 term "boot interrupts" to describe this mechan
20 protocol describes this in-band legacy wire-in
21 I/O devices to signal PCI-style level interrup
22 describe problems with the Core IO handling of
23 PCH and mitigation within BIOS and the OS.
24
25
26 Issue
27 =====
28
29 When in-band legacy INTx messages are forwarde
30 trigger a new interrupt for which the OS likel
31 interrupt goes unhandled over time, they are t
32 Spurious Interrupts. The IRQ will be disabled
33 reaches a specific count with the error "nobod
34 now prevents valid usage by an existing interr
35 the IRQ line::
36
37 irq 19: nobody cared (try booting with the "
38 CPU: 0 PID: 2988 Comm: irq/34-nipalk Tainted
39 Hardware name: National Instruments NI PXIe-
40 Call Trace:
41
42 <IRQ>
43 ? dump_stack+0x46/0x5e
44 ? __report_bad_irq+0x2e/0xb0
45 ? note_interrupt+0x242/0x290
46 ? nNIKAL100_memoryRead16+0x8/0x10 [nikal]
47 ? handle_irq_event_percpu+0x55/0x70
48 ? handle_irq_event+0x4f/0x80
49 ? handle_fasteoi_irq+0x81/0x180
50 ? handle_irq+0x1c/0x30
51 ? do_IRQ+0x41/0xd0
52 ? common_interrupt+0x84/0x84
53 </IRQ>
54
55 handlers:
56 irq_default_primary_handler threaded usb_hcd
57 Disabling IRQ #19
58
59
60 Conditions
61 ==========
62
63 The use of threaded interrupts is the most lik
64 this problem today. Threaded interrupts may no
65 handler wakes. These "one shot" conditions mea
66 needs to keep the interrupt line masked until
67 Especially when dealing with high data rate in
68 run to completion; otherwise some handlers wil
69 since the interrupt of the issuing device is s
70
71 Affected Chipsets
72 =================
73
74 The legacy interrupt forwarding mechanism exis
75 devices including but not limited to chipsets
76 Intel. Changes made through the mitigations be
77 drivers/pci/quirks.c
78
79 Starting with ICX there are no longer any IO-A
80 devices. IO-APIC is only in the PCH. Devices
81 PCIe Root Ports will use native MSI/MSI-X mech
82
83 Mitigations
84 ===========
85
86 The mitigations take the form of PCI quirks. T
87 first identify and make use of a means to disa
88 In such a case a quirk to disable boot interru
89 added. [1]_
90
91 Intel® 6300ESB I/O Controller Hub
92 Alternate Base Address Register:
93 BIE: Boot Interrupt Enable
94
95 == ===========================
96 0 Boot interrupt is enabled.
97 1 Boot interrupt is disabled.
98 == ===========================
99
100 Intel® Sandy Bridge through Sky Lake based Xe
101 Coherent Interface Protocol Interrupt Contro
102 dis_intx_route2pch/dis_intx_route2ich/dis_i
103 When this bit is set. Local INTx mes
104 Intel® Quick Data DMA/PCI Express p
105 PCH - they are either converted into
106 (if the IO-APIC mask bit is clear in
107 or cause no further action (when mas
108
109 In the absence of a way to directly disable th
110 has been to make use of PCI Interrupt pin to I
111 purposes of redirecting the interrupt handler
112 line by default. Therefore, on chipsets where
113 disabled, the Linux kernel will reroute the va
114 interrupt. This redirection of the handler wil
115 the spurious interrupt detection which would o
116 line due to excessive unhandled counts. [2]_
117
118 The config option X86_REROUTE_FOR_BROKEN_BOOT_
119 disable) the redirection of the interrupt hand
120 line. The option can be overridden by either p
121 pci=noioapicreroute. [3]_
122
123
124 More Documentation
125 ==================
126
127 There is an overview of the legacy interrupt h
128 (6300ESB and 6700PXH below). While largely the
129 into the evolution of its handling with chipse
130
131 Example of disabling of the boot interrupt
132 ------------------------------------------
133
134 - Intel® 6300ESB I/O Controller Hub (Do
135 5.7.3 Boot Interrupt
136 https://www.intel.com/content/dam/doc/
137
138 - Intel® Xeon® Processor E5-1600/2400/
139 Datasheet - Volume 2: Registers (Docum
140 6.6.41 cipintrc Coherent Interface Pro
141 https://www.intel.com/content/dam/www/
142
143 Example of handler rerouting
144 ----------------------------
145
146 - Intel® 6700PXH 64-bit PCI Hub (Docume
147 2.15.2 PCI Express Legacy INTx Support
148 https://www.intel.com/content/dam/doc/
149
150
151 If you have any legacy PCI interrupt questions
152
153 Cheers,
154 Sean V Kelley
155 sean.v.kelley@linux.intel.com
156
157 .. [1] https://lore.kernel.org/r/1213194918190
158 .. [2] https://lore.kernel.org/r/1213194918209
159 .. [3] https://lore.kernel.org/r/487C8EA7.6020
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