1 L1D Flushing 1 L1D Flushing
2 ============ 2 ============
3 3
4 With an increasing number of vulnerabilities b 4 With an increasing number of vulnerabilities being reported around data
5 leaks from the Level 1 Data cache (L1D) the ke 5 leaks from the Level 1 Data cache (L1D) the kernel provides an opt-in
6 mechanism to flush the L1D cache on context sw 6 mechanism to flush the L1D cache on context switch.
7 7
8 This mechanism can be used to address e.g. CVE 8 This mechanism can be used to address e.g. CVE-2020-0550. For applications
9 the mechanism keeps them safe from vulnerabili 9 the mechanism keeps them safe from vulnerabilities, related to leaks
10 (snooping of) from the L1D cache. 10 (snooping of) from the L1D cache.
11 11
12 12
13 Related CVEs 13 Related CVEs
14 ------------ 14 ------------
15 The following CVEs can be addressed by this 15 The following CVEs can be addressed by this
16 mechanism 16 mechanism
17 17
18 ============= ====================== 18 ============= ======================== ==================
19 CVE-2020-0550 Improper Data Forwardi 19 CVE-2020-0550 Improper Data Forwarding OS related aspects
20 ============= ====================== 20 ============= ======================== ==================
21 21
22 Usage Guidelines 22 Usage Guidelines
23 ---------------- 23 ----------------
24 24
25 Please see document: :ref:`Documentation/users 25 Please see document: :ref:`Documentation/userspace-api/spec_ctrl.rst
26 <set_spec_ctrl>` for details. 26 <set_spec_ctrl>` for details.
27 27
28 **NOTE**: The feature is disabled by default, 28 **NOTE**: The feature is disabled by default, applications need to
29 specifically opt into the feature to enable it 29 specifically opt into the feature to enable it.
30 30
31 Mitigation 31 Mitigation
32 ---------- 32 ----------
33 33
34 When PR_SET_L1D_FLUSH is enabled for a task a 34 When PR_SET_L1D_FLUSH is enabled for a task a flush of the L1D cache is
35 performed when the task is scheduled out and t 35 performed when the task is scheduled out and the incoming task belongs to a
36 different process and therefore to a different 36 different process and therefore to a different address space.
37 37
38 If the underlying CPU supports L1D flushing in 38 If the underlying CPU supports L1D flushing in hardware, the hardware
39 mechanism is used, software fallback for the m 39 mechanism is used, software fallback for the mitigation, is not supported.
40 40
41 Mitigation control on the kernel command line 41 Mitigation control on the kernel command line
42 --------------------------------------------- 42 ---------------------------------------------
43 43
44 The kernel command line allows to control the 44 The kernel command line allows to control the L1D flush mitigations at boot
45 time with the option "l1d_flush=". The valid a 45 time with the option "l1d_flush=". The valid arguments for this option are:
46 46
47 ============ ============================== 47 ============ =============================================================
48 on Enables the prctl interface, a 48 on Enables the prctl interface, applications trying to use
49 the prctl() will fail with an 49 the prctl() will fail with an error if l1d_flush is not
50 enabled 50 enabled
51 ============ ============================== 51 ============ =============================================================
52 52
53 By default the mechanism is disabled. 53 By default the mechanism is disabled.
54 54
55 Limitations 55 Limitations
56 ----------- 56 -----------
57 57
58 The mechanism does not mitigate L1D data leaks 58 The mechanism does not mitigate L1D data leaks between tasks belonging to
59 different processes which are concurrently exe 59 different processes which are concurrently executing on sibling threads of
60 a physical CPU core when SMT is enabled on the 60 a physical CPU core when SMT is enabled on the system.
61 61
62 This can be addressed by controlled placement 62 This can be addressed by controlled placement of processes on physical CPU
63 cores or by disabling SMT. See the relevant ch 63 cores or by disabling SMT. See the relevant chapter in the L1TF mitigation
64 document: :ref:`Documentation/admin-guide/hw-v 64 document: :ref:`Documentation/admin-guide/hw-vuln/l1tf.rst <smt_control>`.
65 65
66 **NOTE** : The opt-in of a task for L1D flushi 66 **NOTE** : The opt-in of a task for L1D flushing works only when the task's
67 affinity is limited to cores running in non-SM 67 affinity is limited to cores running in non-SMT mode. If a task which
68 requested L1D flushing is scheduled on a SMT-e 68 requested L1D flushing is scheduled on a SMT-enabled core the kernel sends
69 a SIGBUS to the task. 69 a SIGBUS to the task.
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