1 ====================================
2 Arm Network-on Chip Interconnect PMU
3 ====================================
4
5 NI-700 and friends implement a distinct PMU fo
6 interconnect. Correspondingly, the driver expo
7 arm_ni_<x>_cd_<y>, where <x> is an (arbitrary)
8 the clock domain ID within that particular ins
9 exist within a system, the PMU devices can be
10 hardware instance via sysfs parentage.
11
12 Each PMU exposes base event aliases for the in
13 domain. These require qualifying with the "eve
14 to specify the event code to count and the int
15 (per the configured hardware ID as reflected i
16 The exception is the "cycles" alias for the PM
17 with the PMU node type and needs no further qu
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