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2 Arm Network-on Chip Interconnect PMU 2 Arm Network-on Chip Interconnect PMU
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4 4
5 NI-700 and friends implement a distinct PMU fo 5 NI-700 and friends implement a distinct PMU for each clock domain within the
6 interconnect. Correspondingly, the driver expo 6 interconnect. Correspondingly, the driver exposes multiple PMU devices named
7 arm_ni_<x>_cd_<y>, where <x> is an (arbitrary) 7 arm_ni_<x>_cd_<y>, where <x> is an (arbitrary) instance identifier and <y> is
8 the clock domain ID within that particular ins 8 the clock domain ID within that particular instance. If multiple NI instances
9 exist within a system, the PMU devices can be 9 exist within a system, the PMU devices can be correlated with the underlying
10 hardware instance via sysfs parentage. 10 hardware instance via sysfs parentage.
11 11
12 Each PMU exposes base event aliases for the in 12 Each PMU exposes base event aliases for the interface types present in its clock
13 domain. These require qualifying with the "eve 13 domain. These require qualifying with the "eventid" and "nodeid" parameters
14 to specify the event code to count and the int 14 to specify the event code to count and the interface at which to count it
15 (per the configured hardware ID as reflected i 15 (per the configured hardware ID as reflected in the xxNI_NODE_INFO register).
16 The exception is the "cycles" alias for the PM 16 The exception is the "cycles" alias for the PMU cycle counter, which is encoded
17 with the PMU node type and needs no further qu 17 with the PMU node type and needs no further qualification.
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