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2 Freescale i.MX8 DDR Performance Monitoring Uni 2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
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4 4
5 There are no performance counters inside the D 5 There are no performance counters inside the DRAM controller, so performance
6 signals are brought out to the edge of the con 6 signals are brought out to the edge of the controller where a set of 4 x 32 bit
7 counters is implemented. This is controlled by !! 7 counters is implemented. This is controlled by the CSV modes programed in counter
8 control register which causes a large number o 8 control register which causes a large number of PERF signals to be generated.
9 9
10 Selection of the value for each counter is don 10 Selection of the value for each counter is done via the config registers. There
11 is one register for each counter. Counter 0 is 11 is one register for each counter. Counter 0 is special in that it always counts
12 “time” and when expired causes a lock on i 12 “time” and when expired causes a lock on itself and the other counters and an
13 interrupt is raised. If any other counter over 13 interrupt is raised. If any other counter overflows, it continues counting, and
14 no interrupt is raised. 14 no interrupt is raised.
15 15
16 The "format" directory describes format of the !! 16 The "format" directory describes format of the config (event ID) and config1
17 (AXI filter setting) fields of the perf_event_ !! 17 (AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/
18 devices/imx8_ddr0/format/. The "events" direct 18 devices/imx8_ddr0/format/. The "events" directory describes the events types
19 hardware supported that can be used with perf 19 hardware supported that can be used with perf tool, see /sys/bus/event_source/
20 devices/imx8_ddr0/events/. The "caps" director !! 20 devices/imx8_ddr0/events/.
21 in DDR PMU, see /sys/bus/events_source/devices !! 21 e.g.::
22 <<
23 .. code-block:: bash <<
24 <<
25 perf stat -a -e imx8_ddr0/cycles/ cmd 22 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_d 23 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
27 24
28 AXI filtering is only used by CSV modes 0x41 ( 25 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
29 to count reading or writing matches filter set 26 to count reading or writing matches filter setting. Filter setting is various
30 from different DRAM controller implementations 27 from different DRAM controller implementations, which is distinguished by quirks
31 in the driver. You also can dump info from use !! 28 in the driver.
32 type of AXI filter (filter, enhanced_filter an <<
33 un-supported, and value 1 for supported. <<
34 29
35 * With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, !! 30 * With DDR_CAP_AXI_ID_FILTER quirk.
36 Filter is defined with two configuration par 31 Filter is defined with two configuration parts:
37 --AXI_ID defines AxID matching value. 32 --AXI_ID defines AxID matching value.
38 --AXI_MASKING defines which bits of AxID are 33 --AXI_MASKING defines which bits of AxID are meaningful for the matching.
39 !! 34 0：corresponding bit is masked.
40 - 0: corresponding bit is masked. !! 35 1: corresponding bit is not masked, i.e. used to do the matching.
41 - 1: corresponding bit is not masked, i. <<
42 36
43 AXI_ID and AXI_MASKING are mapped on DPCR1 r 37 AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter.
44 When non-masked bits are matching correspond 38 When non-masked bits are matching corresponding AXI_ID bits then counter is
45 incremented. Perf counter is incremented if: !! 39 incremented. Perf counter is incremented if
46 !! 40 AxID && AXI_MASKING == AXI_ID && AXI_MASKING
47 AxID && AXI_MASKING == AXI_ID && AXI_M <<
48 41
49 This filter doesn't support filter different 42 This filter doesn't support filter different AXI ID for axid-read and axid-write
50 event at the same time as this filter is sha 43 event at the same time as this filter is shared between counters.
51 !! 44 e.g.::
52 .. code-block:: bash !! 45 perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
53 !! 46 perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
54 perf stat -a -e imx8_ddr0/axid-read,axi_ !! 47
55 perf stat -a -e imx8_ddr0/axid-write,axi !! 48 NOTE: axi_mask is inverted in userspace(i.e. set bits are bits to mask), and
56 !! 49 it will be reverted in driver automatically. so that the user can just specify
57 .. note:: !! 50 axi_id to monitor a specific id, rather than having to specify axi_mask.
58 !! 51 e.g.::
59 axi_mask is inverted in userspace(i.e. s <<
60 it will be reverted in driver automatica <<
61 axi_id to monitor a specific id, rather <<
62 <<
63 .. code-block:: bash <<
64 <<
65 perf stat -a -e imx8_ddr0/axid-read,ax 52 perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12
66 <<
67 * With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(fi <<
68 This is an extension to the DDR_CAP_AXI_ID_F <<
69 counting the number of bytes (as opposed to <<
70 read and write transactions concurrently wit <<
71 <<
72 * With DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quir <<
73 There is a limitation in previous AXI filter <<
74 at the same time as the filter is shared bet <<
75 extension of AXI ID filter. One improvement <<
76 filter, means that it supports concurrently <<
77 improvement is that counter 1-3 supports AXI <<
78 selecting address channel or data channel. <<
79 <<
80 Filter is defined with 2 configuration regis <<
81 --Counter N MASK COMP register - including A <<
82 --Counter N MUX CNTL register - including AX <<
83 <<
84 - 0: address channel <<
85 - 1: data channel <<
86 <<
87 PMU in DDR subsystem, only one single port0 <<
88 which should be 0. <<
89 <<
90 .. code-block:: bash <<
91 <<
92 perf stat -a -e imx8_ddr0/axid-read,axi_ <<
93 perf stat -a -e imx8_ddr0/axid-write,axi <<
94 <<
95 .. note:: <<
96 <<
97 axi_channel is inverted in userspace, an <<
98 automatically. So that users do not need <<
99 monitor data channel from DDR transactio <<
100 meaningful. <<
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