1 ============================================== 1 ===================================================================== 2 Qualcomm Technologies Level-2 Cache Performanc 2 Qualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU) 3 ============================================== 3 ===================================================================== 4 4 5 This driver supports the L2 cache clusters fou 5 This driver supports the L2 cache clusters found in Qualcomm Technologies 6 Centriq SoCs. There are multiple physical L2 c 6 Centriq SoCs. There are multiple physical L2 cache clusters, each with their 7 own PMU. Each cluster has one or more CPUs ass 7 own PMU. Each cluster has one or more CPUs associated with it. 8 8 9 There is one logical L2 PMU exposed, which agg 9 There is one logical L2 PMU exposed, which aggregates the results from 10 the physical PMUs. 10 the physical PMUs. 11 11 12 The driver provides a description of its avail 12 The driver provides a description of its available events and configuration 13 options in sysfs, see /sys/bus/event_source/de !! 13 options in sysfs, see /sys/devices/l2cache_0. 14 14 15 The "format" directory describes the format of 15 The "format" directory describes the format of the events. 16 16 17 Events can be envisioned as a 2-dimensional ar 17 Events can be envisioned as a 2-dimensional array. Each column represents 18 a group of events. There are 8 groups. Only on 18 a group of events. There are 8 groups. Only one entry from each 19 group can be in use at a time. If multiple eve 19 group can be in use at a time. If multiple events from the same group 20 are specified, the conflicting events cannot b 20 are specified, the conflicting events cannot be counted at the same time. 21 21 22 Events are specified as 0xCCG, where CC is 2 h 22 Events are specified as 0xCCG, where CC is 2 hex digits specifying 23 the code (array row) and G specifies the group 23 the code (array row) and G specifies the group (column) 0-7. 24 24 25 In addition there is a cycle counter event spe 25 In addition there is a cycle counter event specified by the value 0xFE 26 which is outside the above scheme. 26 which is outside the above scheme. 27 27 28 The driver provides a "cpumask" sysfs attribut 28 The driver provides a "cpumask" sysfs attribute which contains a mask 29 consisting of one CPU per cluster which will b 29 consisting of one CPU per cluster which will be used to handle all the PMU 30 events on that cluster. 30 events on that cluster. 31 31 32 Examples for use with perf:: 32 Examples for use with perf:: 33 33 34 perf stat -e l2cache_0/config=0x001/,l2cache 34 perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1 35 35 36 perf stat -e l2cache_0/config=0xfe/ -C 2 sle 36 perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1 37 37 38 The driver does not support sampling, therefor 38 The driver does not support sampling, therefore "perf record" will 39 not work. Per-task perf sessions are not suppo 39 not work. Per-task perf sessions are not supported.
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