1 ==========
2 Interrupts
3 ==========
4
5 2.5.2-rmk5:
6 This is the first kernel that contains a maj
7 major architecture-specific subsystems.
8
9 Firstly, it contains some pretty major changes
10 MMU TLB. Each MMU TLB variant is now handled
11 we have TLB v3, TLB v4 (without write buffer),
12 and finally TLB v4 (with write buffer, with I
13 There is more assembly code inside each of the
14 allow more flexible TLB handling for the futur
15
16 Secondly, the IRQ subsystem.
17
18 The 2.5 kernels will be having major changes t
19 Unfortunately, this means that machine types t
20 array (basically all machine types) will break
21 machine type that we currently have.
22
23 Lets take an example. On the Assabet with Nep
24
25 GPIO25 IRR:2
26 SA1100 ------------> Neponset --------
27 IIR:1
28 --------
29 IIR:0
30 --------
31
32 The way stuff currently works, all SA1111 inte
33 exclusive of each other - if you're processing
34 SA1111 and another comes in, you have to wait
35 finish processing before you can service the n
36 IDE PIO-based interrupt on the SA1111 excludes
37 SMC9196 interrupts until it has finished trans
38 data, which can be a long time. Note also tha
39 SA1111 IRQ handler, SA1111 IRQs can hold off S
40
41
42 The new approach brings several new ideas...
43
44 We introduce the concept of a "parent" and a "
45 to the Neponset handler, the "parent" is GPIO2
46 are SA1111, SMC9196 and USAR.
47
48 We also bring the idea of an IRQ "chip" (mainl
49 the irqdesc array). This doesn't have to be a
50 SA11x0 IRQs are handled by two separate "chip"
51 GPIO0-10, and another for all the rest. It is
52 the various operations (maybe this'll change t
53 This structure has the following operations::
54
55 struct irqchip {
56 /*
57 * Acknowledge the IRQ.
58 * If this is a level-based IRQ, the
59 * as well.
60 */
61 void (*ack)(unsigned int irq);
62 /*
63 * Mask the IRQ in hardware.
64 */
65 void (*mask)(unsigned int irq);
66 /*
67 * Unmask the IRQ in hardware.
68 */
69 void (*unmask)(unsigned int irq);
70 /*
71 * Re-run the IRQ
72 */
73 void (*rerun)(unsigned int irq);
74 /*
75 * Set the type of the IRQ.
76 */
77 int (*type)(unsigned int irq, unsign
78 };
79
80 ack
81 - required. May be the same function a
82 handled by do_level_IRQ.
83 mask
84 - required.
85 unmask
86 - required.
87 rerun
88 - optional. Not required if you're usi
89 IRQs that use this 'irqchip'. Genera
90 the hardware IRQ if possible. If not
91 directly.
92 type
93 - optional. If you don't support chang
94 it should be null so people can detec
95 set the IRQ type.
96
97 For each IRQ, we keep the following informatio
98
99 - "disable" depth (number of disable_i
100 - flags indicating what we can do with
101 noautounmask) as before
102 - status of the IRQ (probing, enable,
103 - chip
104 - per-IRQ handler
105 - irqaction structure list
106
107 The handler can be one of the 3 standard handl
108 "simple", or your own specific handler if you
109
110 The "level" handler is what we currently have
111 "edge" knows about the brokenness of such IRQ
112 need to leave the hardware IRQ enabled while p
113 further IRQ events should the IRQ happen again
114 "simple" handler is very basic, and does not p
115 manipulation, nor state tracking. This is use
116 SMC9196 and USAR above.
117
118 So, what's changed?
119 ===================
120
121 1. Machine implementations must not write to t
122
123 2. New functions to manipulate the irqdesc arr
124 to be useful only to machine specific code.
125 only be used by machine specific code, but
126 absolutely necessary.
127
128 set_irq_chip(irq,chip)
129 Set the mask/unmask methods fo
130
131 set_irq_handler(irq,handler)
132 Set the handler for this IRQ (
133
134 set_irq_chained_handler(irq,handler)
135 Set a "chained" handler for th
136 enables this IRQ (eg, Neponset
137
138 set_irq_flags(irq,flags)
139 Set the valid/probe/noautoenab
140
141 set_irq_type(irq,type)
142 Set active the IRQ edge(s)/lev
143 SA1111 INTPOL manipulation, an
144 function. Type should be one
145 <linux/irq.h>
146
147 3. set_GPIO_IRQ_edge() is obsolete, and should
148
149 4. Direct access to SA1111 INTPOL is deprecate
150
151 5. A handler is expected to perform any necess
152 parent IRQ via the correct chip specific fu
153 the SA1111 is directly connected to a SA111
154 acknowledge the SA1110 IRQ each time you re
155
156 6. For any child which doesn't have its own IR
157 (eg, SMC9196), the handler must mask or ack
158 while the child handler is called, and the
159 "simple" handler (not "edge" nor "level").
160 the parent IRQ should be unmasked, and the
161 be re-checked for pending events. (see the
162 details).
163
164 7. fixup_irq() is gone, as is `arch/arm/mach-*
165
166 Please note that this will not solve all probl
167 hardware based. Mixing level-based and edge-b
168 parent signal (eg neponset) is one such area w
169 solution can't provide the full answer to low
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