Linux/Documentation/arch/arm64/booting.rst

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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1 ===================== !! 1 .. SPDX-License-Identifier: GPL-2.0 2 Booting AArch64 Linux << 3 ===================== << 4 2 5 Author: Will Deacon <will.deacon@arm.com> !! 3 BMIPS DeviceTree Booting 6 << 7 Date : 07 September 2012 << 8 << 9 This document is based on the ARM booting docu << 10 is relevant to all public releases of the AArc << 11 << 12 The AArch64 exception model is made up of a nu << 13 (EL0 - EL3), with EL0, EL1 and EL2 having a se << 14 counterpart. EL2 is the hypervisor level, EL3 << 15 level and exists only in secure mode. Both are << 16 << 17 For the purposes of this document, we will use << 18 simply to define all software that executes on << 19 is passed to the Linux kernel. This may inclu << 20 hypervisor code, or it may just be a handful o << 21 preparing a minimal boot environment. << 22 << 23 Essentially, the boot loader should provide (a << 24 following: << 25 << 26 1. Setup and initialise the RAM << 27 2. Setup the device tree << 28 3. Decompress the kernel image << 29 4. Call the kernel image << 30 << 31 << 32 1. Setup and initialise RAM << 33 --------------------------- << 34 << 35 Requirement: MANDATORY << 36 << 37 The boot loader is expected to find and initia << 38 kernel will use for volatile data storage in t << 39 this in a machine dependent manner. (It may u << 40 to automatically locate and size all RAM, or i << 41 the RAM in the machine, or any other method th << 42 sees fit.) << 43 << 44 << 45 2. Setup the device tree << 46 ------------------------- << 47 << 48 Requirement: MANDATORY << 49 << 50 The device tree blob (dtb) must be placed on a << 51 not exceed 2 megabytes in size. Since the dtb << 52 using blocks of up to 2 megabytes in size, it << 53 any 2M region which must be mapped with any sp << 54 << 55 NOTE: versions prior to v4.2 also require that << 56 the 512 MB region starting at text_offset byte << 57 << 58 3. Decompress the kernel image << 59 ------------------------------ << 60 << 61 Requirement: OPTIONAL << 62 << 63 The AArch64 kernel does not currently provide << 64 therefore requires decompression (gzip etc.) t << 65 loader if a compressed Image target (e.g. Imag << 66 bootloaders that do not implement this require << 67 Image target is available instead. << 68 << 69 << 70 4. Call the kernel image << 71 ------------------------ 4 ------------------------ 72 5 73 Requirement: MANDATORY !! 6 Some bootloaders only support a single entry point, at the start of the 74 !! 7 kernel image. Other bootloaders will jump to the ELF start address. 75 The decompressed kernel image contains a 64-by !! 8 Both schemes are supported; CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y, 76 !! 9 so the first instruction immediately jumps to kernel_entry(). 77 u32 code0; /* Executable << 78 u32 code1; /* Executable << 79 u64 text_offset; /* Image load << 80 u64 image_size; /* Effective I << 81 u64 flags; /* kernel flag << 82 u64 res2 = 0; /* reserved */ << 83 u64 res3 = 0; /* reserved */ << 84 u64 res4 = 0; /* reserved */ << 85 u32 magic = 0x644d5241; /* Magic numbe << 86 u32 res5; /* reserved (u << 87 << 88 << 89 Header notes: << 90 << 91 - As of v3.17, all fields are little endian un << 92 << 93 - code0/code1 are responsible for branching to << 94 << 95 - when booting through EFI, code0/code1 are in << 96 res5 is an offset to the PE header and the P << 97 entry point (efi_stub_entry). When the stub << 98 jumps to code0 to resume the normal boot pro << 99 << 100 - Prior to v3.17, the endianness of text_offse << 101 these cases image_size is zero and text_offs << 102 endianness of the kernel. Where image_size << 103 little-endian and must be respected. Where << 104 text_offset can be assumed to be 0x80000. << 105 << 106 - The flags field (introduced in v3.17) is a l << 107 composed as follows: << 108 << 109 ============= ============================== << 110 Bit 0 Kernel endianness. 1 if BE, 0 << 111 Bit 1-2 Kernel Page size. << 112 << 113 * 0 - Unspecified. << 114 * 1 - 4K << 115 * 2 - 16K << 116 * 3 - 64K << 117 Bit 3 Kernel physical placement << 118 << 119 0 << 120 2MB aligned base sho << 121 to the base of DRAM, << 122 accessible via the l << 123 1 << 124 2MB aligned base suc << 125 counted from the sta << 126 the 48-bit addressab << 127 Bits 4-63 Reserved. << 128 ============= ============================== << 129 << 130 - When image_size is zero, a bootloader should << 131 memory as possible free for use by the kerne << 132 end of the kernel image. The amount of space << 133 depending on selected features, and is effec << 134 << 135 The Image must be placed text_offset bytes fro << 136 address anywhere in usable system RAM and call << 137 between the 2 MB aligned base address and the << 138 special significance to the kernel, and may be << 139 At least image_size bytes from the start of th << 140 use by the kernel. << 141 NOTE: versions prior to v4.6 cannot make use o << 142 physical offset of the Image so it is recommen << 143 placed as close as possible to the start of sy << 144 << 145 If an initrd/initramfs is passed to the kernel << 146 entirely within a 1 GB aligned physical memory << 147 size that fully covers the kernel Image as wel << 148 << 149 Any memory described to the kernel (even that << 150 image) which is not marked as reserved from th << 151 memreserve region in the device tree) will be << 152 the kernel. << 153 << 154 Before jumping into the kernel, the following << 155 << 156 - Quiesce all DMA capable devices so that memo << 157 corrupted by bogus network packets or disk d << 158 you many hours of debug. << 159 << 160 - Primary CPU general-purpose register setting << 161 << 162 - x0 = physical address of device tree blo << 163 - x1 = 0 (reserved for future use) << 164 - x2 = 0 (reserved for future use) << 165 - x3 = 0 (reserved for future use) << 166 << 167 - CPU mode << 168 << 169 All forms of interrupts must be masked in PS << 170 IRQ and FIQ). << 171 The CPU must be in non-secure state, either << 172 to have access to the virtualisation extensi << 173 << 174 - Caches, MMUs << 175 << 176 The MMU must be off. << 177 << 178 The instruction cache may be on or off, and << 179 entries corresponding to the loaded kernel i << 180 << 181 The address range corresponding to the loade << 182 cleaned to the PoC. In the presence of a sys << 183 coherent masters with caches enabled, this w << 184 cache maintenance by VA rather than set/way << 185 System caches which respect the architected << 186 operations must be configured and may be ena << 187 System caches which do not respect architect << 188 operations (not recommended) must be configu << 189 << 190 - Architected timers << 191 << 192 CNTFRQ must be programmed with the timer fre << 193 be programmed with a consistent value on all << 194 kernel at EL1, CNTHCTL_EL2 must have EL1PCTE << 195 available. << 196 << 197 - Coherency << 198 << 199 All CPUs to be booted by the kernel must be << 200 domain on entry to the kernel. This may req << 201 initialisation to enable the receiving of ma << 202 each CPU. << 203 << 204 - System registers << 205 << 206 All writable architected system registers at << 207 level where the kernel image will be entered << 208 software at a higher exception level to prev << 209 state. << 210 << 211 For all systems: << 212 - If EL3 is present: << 213 << 214 - SCR_EL3.FIQ must have the same value acr << 215 executing on. << 216 - The value of SCR_EL3.FIQ must be the sam << 217 time whenever the kernel is executing. << 218 << 219 - If EL3 is present and the kernel is entere << 220 << 221 - SCR_EL3.HCE (bit 8) must be initialised << 222 << 223 For systems with a GICv3 interrupt controlle << 224 - If EL3 is present: << 225 << 226 - ICC_SRE_EL3.Enable (bit 3) must be ini << 227 - ICC_SRE_EL3.SRE (bit 0) must be initia << 228 - ICC_CTLR_EL3.PMHE (bit 6) must be set << 229 all CPUs the kernel is executing on, a << 230 for the lifetime of the kernel. << 231 << 232 - If the kernel is entered at EL1: << 233 << 234 - ICC.SRE_EL2.Enable (bit 3) must be ini << 235 - ICC_SRE_EL2.SRE (bit 0) must be initia << 236 << 237 - The DT or ACPI tables must describe a GICv << 238 << 239 For systems with a GICv3 interrupt controlle << 240 compatibility (v2) mode: << 241 << 242 - If EL3 is present: << 243 << 244 ICC_SRE_EL3.SRE (bit 0) must be initiali << 245 << 246 - If the kernel is entered at EL1: << 247 << 248 ICC_SRE_EL2.SRE (bit 0) must be initiali << 249 << 250 - The DT or ACPI tables must describe a GICv << 251 << 252 For CPUs with pointer authentication functio << 253 << 254 - If EL3 is present: << 255 << 256 - SCR_EL3.APK (bit 16) must be initialised << 257 - SCR_EL3.API (bit 17) must be initialised << 258 << 259 - If the kernel is entered at EL1: << 260 << 261 - HCR_EL2.APK (bit 40) must be initialised << 262 - HCR_EL2.API (bit 41) must be initialised << 263 << 264 For CPUs with Activity Monitors Unit v1 (AMU << 265 << 266 - If EL3 is present: << 267 << 268 - CPTR_EL3.TAM (bit 30) must be initialise << 269 - CPTR_EL2.TAM (bit 30) must be initialise << 270 - AMCNTENSET0_EL0 must be initialised to 0 << 271 - AMCNTENSET1_EL0 must be initialised to a << 272 having 0b1 set for the corresponding bit << 273 counters present. << 274 << 275 - If the kernel is entered at EL1: << 276 << 277 - AMCNTENSET0_EL0 must be initialised to 0 << 278 - AMCNTENSET1_EL0 must be initialised to a << 279 having 0b1 set for the corresponding bit << 280 counters present. << 281 << 282 For CPUs with the Fine Grained Traps (FEAT_F << 283 << 284 - If EL3 is present and the kernel is entere << 285 << 286 - SCR_EL3.FGTEn (bit 27) must be initialis << 287 << 288 For CPUs with support for HCRX_EL2 (FEAT_HCX << 289 << 290 - If EL3 is present and the kernel is entere << 291 << 292 - SCR_EL3.HXEn (bit 38) must be initialise << 293 << 294 For CPUs with Advanced SIMD and floating poi << 295 << 296 - If EL3 is present: << 297 << 298 - CPTR_EL3.TFP (bit 10) must be initialise << 299 << 300 - If EL2 is present and the kernel is entere << 301 << 302 - CPTR_EL2.TFP (bit 10) must be initialise << 303 << 304 For CPUs with the Scalable Vector Extension << 305 << 306 - if EL3 is present: << 307 << 308 - CPTR_EL3.EZ (bit 8) must be initialised << 309 << 310 - ZCR_EL3.LEN must be initialised to the s << 311 kernel is executed on. << 312 << 313 - If the kernel is entered at EL1 and EL2 is << 314 << 315 - CPTR_EL2.TZ (bit 8) must be initialised << 316 << 317 - CPTR_EL2.ZEN (bits 17:16) must be initia << 318 << 319 - ZCR_EL2.LEN must be initialised to the s << 320 kernel will execute on. << 321 << 322 For CPUs with the Scalable Matrix Extension << 323 << 324 - If EL3 is present: << 325 << 326 - CPTR_EL3.ESM (bit 12) must be initialise << 327 << 328 - SCR_EL3.EnTP2 (bit 41) must be initialis << 329 << 330 - SMCR_EL3.LEN must be initialised to the << 331 kernel will execute on. << 332 << 333 - If the kernel is entered at EL1 and EL2 is << 334 << 335 - CPTR_EL2.TSM (bit 12) must be initialise << 336 << 337 - CPTR_EL2.SMEN (bits 25:24) must be initi << 338 << 339 - SCTLR_EL2.EnTP2 (bit 60) must be initial << 340 << 341 - SMCR_EL2.LEN must be initialised to the << 342 kernel will execute on. << 343 << 344 - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be << 345 << 346 - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be << 347 << 348 - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be << 349 << 350 - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be << 351 << 352 For CPUs with the Scalable Matrix Extension << 353 << 354 - If EL3 is present: << 355 << 356 - SMCR_EL3.FA64 (bit 31) must be initialis << 357 << 358 - If the kernel is entered at EL1 and EL2 is << 359 << 360 - SMCR_EL2.FA64 (bit 31) must be initialis << 361 << 362 For CPUs with the Memory Tagging Extension f << 363 << 364 - If EL3 is present: << 365 << 366 - SCR_EL3.ATA (bit 26) must be initialised << 367 << 368 - If the kernel is entered at EL1 and EL2 is << 369 << 370 - HCR_EL2.ATA (bit 56) must be initialised << 371 << 372 For CPUs with the Scalable Matrix Extension << 373 << 374 - If EL3 is present: << 375 << 376 - SMCR_EL3.EZT0 (bit 30) must be initialis << 377 << 378 - If the kernel is entered at EL1 and EL2 is << 379 << 380 - SMCR_EL2.EZT0 (bit 30) must be initialis << 381 << 382 For CPUs with Memory Copy and Memory Set ins << 383 << 384 - If the kernel is entered at EL1 and EL2 is << 385 << 386 - HCRX_EL2.MSCEn (bit 11) must be initiali << 387 << 388 For CPUs with the Extended Translation Contr << 389 << 390 - If EL3 is present: << 391 << 392 - SCR_EL3.TCR2En (bit 43) must be initiali << 393 << 394 - If the kernel is entered at EL1 and EL2 is << 395 << 396 - HCRX_EL2.TCR2En (bit 14) must be initial << 397 << 398 For CPUs with the Stage 1 Permission Indirec << 399 << 400 - If EL3 is present: << 401 << 402 - SCR_EL3.PIEn (bit 45) must be initialise << 403 << 404 - If the kernel is entered at EL1 and EL2 is << 405 << 406 - HFGRTR_EL2.nPIR_EL1 (bit 58) must be ini << 407 << 408 - HFGWTR_EL2.nPIR_EL1 (bit 58) must be ini << 409 << 410 - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be i << 411 << 412 - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be i << 413 << 414 The requirements described above for CPU mode, << 415 timers, coherency and system registers apply t << 416 enter the kernel in the same exception level. << 417 disable traps it is permissible for these trap << 418 those traps are handled transparently by highe << 419 the values documented were set. << 420 << 421 The boot loader is expected to enter the kerne << 422 following manner: << 423 << 424 - The primary CPU must jump directly to the fi << 425 kernel image. The device tree blob passed b << 426 an 'enable-method' property for each cpu nod << 427 enable-methods are described below. << 428 << 429 It is expected that the bootloader will gene << 430 properties and insert them into the blob pri << 431 10 432 - CPUs with a "spin-table" enable-method must !! 11 Similar to the arch/arm case (b), a DT-aware bootloader is expected to 433 property in their cpu node. This property i !! 12 set up the following registers: 434 naturally-aligned 64-bit zero-initalised mem << 435 13 436 These CPUs should spin outside of the kernel !! 14 a0 : 0 437 memory (communicated to the kernel by a /mem << 438 device tree) polling their cpu-release-addr << 439 contained in the reserved region. A wfe ins << 440 to reduce the overhead of the busy-loop and << 441 the primary CPU. When a read of the locatio << 442 cpu-release-addr returns a non-zero value, t << 443 value. The value will be written as a singl << 444 value, so CPUs must convert the read value t << 445 before jumping to it. << 446 15 447 - CPUs with a "psci" enable method should rema !! 16 a1 : 0xffffffff 448 the kernel (i.e. outside of the regions of m << 449 kernel in the memory node, or in a reserved << 450 to the kernel by a /memreserve/ region in th << 451 kernel will issue CPU_ON calls as described << 452 DEN 0022A ("Power State Coordination Interfa << 453 processors") to bring CPUs into the kernel. << 454 17 455 The device tree should contain a 'psci' node !! 18 a2 : Physical pointer to the device tree block (defined in chapter 456 Documentation/devicetree/bindings/arm/psci.y !! 19 II) in RAM. The device tree can be located anywhere in the first >> 20 512MB of the physical address space (0x00000000 - 0x1fffffff), >> 21 aligned on a 64 bit boundary. 457 22 458 - Secondary CPU general-purpose register setti !! 23 Legacy bootloaders do not use this convention, and they do not pass in a >> 24 DT block. In this case, Linux will look for a builtin DTB, selected via >> 25 CONFIG_DT_*. 459 26 460 - x0 = 0 (reserved for future use) !! 27 This convention is defined for 32-bit systems only, as there are not 461 - x1 = 0 (reserved for future use) !! 28 currently any 64-bit BMIPS implementations. 462 - x2 = 0 (reserved for future use) << 463 - x3 = 0 (reserved for future use) <<

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