1 =========================================
2 Freescale QUICC Engine Firmware Uploading
3 =========================================
4
5 (c) 2007 Timur Tabi <timur at freescale.com>,
6 Freescale Semiconductor
7
8 .. Table of Contents
9
10 I - Software License for Firmware
11
12 II - Microcode Availability
13
14 III - Description and Terminology
15
16 IV - Microcode Programming Details
17
18 V - Firmware Structure Layout
19
20 VI - Sample Code for Creating Firmware File
21
22 Revision Information
23 ====================
24
25 November 30, 2007: Rev 1.0 - Initial version
26
27 I - Software License for Firmware
28 =================================
29
30 Each firmware file comes with its own software
31 the particular license, please see the license
32 the firmware.
33
34 II - Microcode Availability
35 ===========================
36
37 Firmware files are distributed through various
38 http://opensource.freescale.com. For other fi
39 your Freescale representative or your operatin
40
41 III - Description and Terminology
42 =================================
43
44 In this document, the term 'microcode' refers
45 integers that compose the actual QE microcode.
46
47 The term 'firmware' refers to a binary blob th
48 well as other data that
49
50 1) describes the microcode's purpose
51 2) describes how and where to upload t
52 3) specifies the values of various reg
53 4) includes additional data for use by
54
55 Firmware files are binary files that contain o
56
57 IV - Microcode Programming Details
58 ===================================
59
60 The QE architecture allows for only one microc
61 RISC processor. To replace any current microc
62 disables the microcode) must be performed firs
63
64 QE microcode is uploaded using the following p
65
66 1) The microcode is placed into I-RAM at a spe
67 IRAM.IADD and IRAM.IDATA registers.
68
69 2) The CERCR.CIR bit is set to 0 or 1, dependi
70 needs split I-RAM. Split I-RAM is only mea
71 QEs with multiple RISC processors, such as
72 allows each processor to run a different mi
73 asymmetric multiprocessing (AMP) system.
74
75 3) The TIBCR trap registers are loaded with th
76 in the microcode.
77
78 4) The RSP.ECCR register is programmed with th
79
80 5) If necessary, device drivers that need the
81 data will use them.
82
83 Virtual Microcode Traps
84
85 These virtual traps are conditional branches i
86 "soft" provisional introduced in the ROMcode i
87 flexibility and save h/w traps If new features
88 being fixed in the RAM package utilizing they
89 structure signals the microcode which of these
90
91 This structure contains 6 words that the appli
92 specific been defined. This table describes t
93
94 --------------------------------------
95 | Offset in | | Desti
96 | array | Protocol | wit
97 --------------------------------------
98 | 0 | Ethernet |
99 | | interworking |
100 --------------------------------------
101 | 4 | ATM |
102 | | interworking |
103 --------------------------------------
104 | 8 | PPP |
105 | | interworking |
106 --------------------------------------
107 | 12 | Ethernet RX |
108 | | Distributor Page |
109 --------------------------------------
110 | 16 | ATM Globtal |
111 | | Params Table |
112 --------------------------------------
113 | 20 | Insert Frame |
114 --------------------------------------
115
116
117 Extended Modes
118
119 This is a double word bit array (64 bits) that
120 which has an impact on the software drivers.
121 and has special instructions for the s/w assoc
122 described in this table::
123
124 --------------------------------------
125 | Bit # | Name | Descriptio
126 --------------------------------------
127 | 0 | General | Indicates th
128 | | push command | given by the
129 | | | assert a spe
130 | | | CECDR = 0x00
131 | | | CECR = 0x01c
132 --------------------------------------
133 | 1 | UCC ATM | Indicates th
134 | | RX INIT | command, the
135 | | push command | command (pus
136 | | | following th
137 | | | command. (Th
138 | | | initializing
139 | | | three host c
140 | | | CECDR = 0x00
141 | | | CECR = 0x01c
142 --------------------------------------
143 | 2 | Add/remove | Indicates th
144 | | command | command: "Ad
145 | | validation | Table" used
146 | | | must issue a
147 | | | CECDR = 0xce
148 | | | CECR = 0x01c
149 --------------------------------------
150 | 3 | General push | Indicates th
151 | | command | some pointer
152 | | | which are us
153 | | | activated.
154 | | | pointers is
155 --------------------------------------
156 | 4 | General push | Indicates th
157 | | command | INIT command
158 | | | for each SNU
159 | | | CECDR = 0x00
160 | | | CECR = 0x7'b
161 | | | 1'b{1
162 --------------------------------------
163 | 5 - 31 | N/A | Reserved, se
164 --------------------------------------
165
166 V - Firmware Structure Layout
167 ==============================
168
169 QE microcode from Freescale is typically provi
170 header file contains macros that define the mi
171 some other data used in uploading that microco
172 do not lend themselves to simple inclusion int
173 the need for a more portable format. This sec
174
175 Instead of distributing a header file, the mic
176 embedded into a binary blob. This blob is pas
177 function, which parses the blob and performs e
178 the microcode.
179
180 All integers are big-endian. See the comments
181 qe_upload_firmware() for up-to-date implementa
182
183 This structure supports versioning, where the
184 embedded into the structure itself. To ensure
185 compatibility, all versions of the structure m
186 structure at the beginning.
187
188 'header' (type: struct qe_header):
189 The 'length' field is the size, in byt
190 including all the microcode embedded i
191 present).
192
193 The 'magic' field is an array of three
194 'Q', 'E', and 'F'. This is an identif
195 structure is a QE Firmware structure.
196
197 The 'version' field is a single byte t
198 structure. If the layout of the struc
199 changed to add support for additional
200 version number should also be changed.
201
202 The 'id' field is a null-terminated string(sui
203 identifies the firmware.
204
205 The 'count' field indicates the number of 'mic
206 must be one and only one 'microcode' structure
207 Therefore, this field also represents the numb
208 SOC.
209
210 The 'soc' structure contains the SOC numbers a
211 the microcode to the SOC itself. Normally, th
212 check the data in this structure with the SOC
213 only upload the microcode if there's a match.
214 made on all platforms.
215
216 Although it is not recommended, you can specif
217 field to skip matching SOCs altogether.
218
219 The 'model' field is a 16-bit number that matc
220 'major' and 'minor' fields are the major and m
221 respectively, of the SOC.
222
223 For example, to match the 8323, revision 1.0::
224
225 soc.model = 8323
226 soc.major = 1
227 soc.minor = 0
228
229 'padding' is necessary for structure alignment
230 'extended_modes' field is aligned on a 64-bit
231
232 'extended_modes' is a bitfield that defines sp
233 impact on the device drivers. Each bit has it
234 instructions for the driver associated with it
235 the QE library and available to any driver tha
236
237 'vtraps' is an array of 8 words that contain v
238 virtual traps. As with 'extended_modes', this
239 library and available to any driver that calls
240
241 'microcode' (type: struct qe_microcode):
242 For each RISC processor there is one '
243 'microcode' structure is for the first
244
245 The 'id' field is a null-terminated st
246 identifies this particular microcode.
247
248 'traps' is an array of 16 words that c
249 for each of the 16 traps. If trap[i]
250 trap is to be ignored (i.e. not writte
251 is written as-is to the TIBCR[i] regis
252 and T_IBP bits if necessary.
253
254 'eccr' is the value to program into th
255
256 'iram_offset' is the offset into IRAM
257 microcode.
258
259 'count' is the number of 32-bit words
260
261 'code_offset' is the offset, in bytes,
262 structure where the microcode itself c
263 microcode binary should be located imm
264 array.
265
266 'major', 'minor', and 'revision' are t
267 version numbers, respectively, of the
268 then these fields are ignored.
269
270 'reserved' is necessary for structure
271 is an array, the 64-bit 'extended_mode
272 on a 64-bit boundary, and this can onl
273 'microcode' is a multiple of 8 bytes.
274 'reserved'.
275
276 After the last microcode is a 32-bit CRC. It
277 this algorithm::
278
279 u32 crc32(const u8 *p, unsigned int len)
280 {
281 unsigned int i;
282 u32 crc = 0;
283
284 while (len--) {
285 crc ^= *p++;
286 for (i = 0; i < 8; i++)
287 crc = (crc >> 1) ^ ((crc &
288 }
289 return crc;
290 }
291
292 VI - Sample Code for Creating Firmware Files
293 ============================================
294
295 A Python program that creates firmware binarie
296 distributed by Freescale can be found on http:
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