1 .. SPDX-License-Identifier: GPL-2.0
2
3 RISC-V Hardware Probing Interface
4 ---------------------------------
5
6 The RISC-V hardware probing interface is based
7 is defined in <asm/hwprobe.h>::
8
9 struct riscv_hwprobe {
10 __s64 key;
11 __u64 value;
12 };
13
14 long sys_riscv_hwprobe(struct riscv_hwprob
15 size_t cpusetsize,
16 unsigned int flags)
17
18 The arguments are split into three groups: an
19 set, and some flags. The key-value pairs are s
20 must prepopulate the key field for each elemen
21 value if the key is recognized. If a key is un
22 will be cleared to -1, and its value set to 0.
23 CPU_SET(3) with size ``cpusetsize`` bytes. For
24 arch, impl), the returned value will only be v
25 have the same value. Otherwise -1 will be retu
26 value returned will be a logical AND of the va
27 Usermode can supply NULL for ``cpus`` and 0 fo
28 all online CPUs. The currently supported flags
29
30 * :c:macro:`RISCV_HWPROBE_WHICH_CPUS`: This fl
31 of sys_riscv_hwprobe(). Instead of populati
32 set of CPUs, the values of each key are give
33 by sys_riscv_hwprobe() to only those which m
34 How matching is done depends on the key type
35 means to be the exact same as the value. Fo
36 means the result of a logical AND of the pai
37 exactly the same as the pair's value. Addit
38 set, then it is initialized to all online CP
39 CPU set returned is the reduction of all the
40 represented with a CPU set of size ``cpusets
41
42 All other flags are reserved for future compat
43
44 On success 0 is returned, on failure a negativ
45
46 The following keys are defined:
47
48 * :c:macro:`RISCV_HWPROBE_KEY_MVENDORID`: Cont
49 as defined by the RISC-V privileged architec
50
51 * :c:macro:`RISCV_HWPROBE_KEY_MARCHID`: Contai
52 defined by the RISC-V privileged architectur
53
54 * :c:macro:`RISCV_HWPROBE_KEY_MIMPLID`: Contai
55 defined by the RISC-V privileged architectur
56
57 * :c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`:
58 user-visible behavior that this kernel suppo
59 are defined:
60
61 * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`
62 rv64ima, as defined by version 2.2 of the
63 privileged ISA, with the following known e
64 added, but only if it can be demonstrated
65
66 * The ``fence.i`` instruction cannot be di
67 programs (it may still be executed in us
68 kernel-controlled mechanism such as the
69
70 * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bi
71 that are compatible with the :c:macro:`RISCV
72 base system behavior.
73
74 * :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and
75 defined by commit cd20cee ("FMIN/FMAX now
76 minimumNumber/maximumNumber, not minNum/ma
77
78 * :c:macro:`RISCV_HWPROBE_IMA_C`: The C exte
79 by version 2.2 of the RISC-V ISA manual.
80
81 * :c:macro:`RISCV_HWPROBE_IMA_V`: The V exte
82 version 1.0 of the RISC-V Vector extension
83
84 * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba
85 supported, as defined in version 1.0 of
86 extensions.
87
88 * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb
89 in version 1.0 of the Bit-Manipulation
90
91 * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs
92 in version 1.0 of the Bit-Manipulation
93
94 * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Z
95 ratified in commit 3dd606f ("Create cmo
96
97 * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc e
98 in version 1.0 of the Bit-Manipulation
99
100 * :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb
101 defined in version 1.0 of the Scalar Cr
102
103 * :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc
104 defined in version 1.0 of the Scalar Cr
105
106 * :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx
107 defined in version 1.0 of the Scalar Cr
108
109 * :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd
110 defined in version 1.0 of the Scalar Cr
111
112 * :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne
113 defined in version 1.0 of the Scalar Cr
114
115 * :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh
116 defined in version 1.0 of the Scalar Cr
117
118 * :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zks
119 defined in version 1.0 of the Scalar Cr
120
121 * :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh
122 defined in version 1.0 of the Scalar Cr
123
124 * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt e
125 in version 1.0 of the Scalar Crypto ISA
126
127 * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvb
128 defined in version 1.0 of the RISC-V Cr
129
130 * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvb
131 defined in version 1.0 of the RISC-V Cr
132
133 * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvk
134 defined in version 1.0 of the RISC-V Cr
135
136 * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvk
137 defined in version 1.0 of the RISC-V Cr
138
139 * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Z
140 defined in version 1.0 of the RISC-V Cr
141
142 * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Z
143 defined in version 1.0 of the RISC-V Cr
144
145 * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Z
146 defined in version 1.0 of the RISC-V Cr
147
148 * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Z
149 defined in version 1.0 of the RISC-V Cr
150
151 * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zv
152 defined in version 1.0 of the RISC-V Cr
153
154 * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvk
155 defined in version 1.0 of the RISC-V Cr
156
157 * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh
158 as defined in the RISC-V ISA manual.
159
160 * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Z
161 supported as defined in the RISC-V ISA
162
163 * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: Th
164 is supported as defined in the RISC-V I
165
166 * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvf
167 defined in the RISC-V Vector manual sta
168 ("Remove draft warnings from Zvfh[min]"
169
170 * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The
171 defined in the RISC-V Vector manual sta
172 ("Remove draft warnings from Zvfh[min]"
173
174 * :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa
175 defined in the RISC-V ISA manual starti
176 ("Zfa is ratified").
177
178 * :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Zts
179 defined in the RISC-V ISA manual starti
180 ("Ztso is now ratified.")
181
182 * :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Za
183 defined in the Atomic Compare-and-Swap
184 from commit 5059e0ca641c ("update to ra
185
186 * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Z
187 defined in the RISC-V Integer Condition
188 manual starting from commit 95cf1f9 ("A
189 during signoff")
190
191 * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`:
192 supported as defined in the RISC-V ISA
193 d8ab5c78c207 ("Zihintpause is ratified"
194
195 * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The V
196 supported, as defined by version 1.0 of th
197
198 * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The V
199 supported, as defined by version 1.0 of th
200
201 * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The V
202 supported, as defined by version 1.0 of th
203
204 * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The V
205 supported, as defined by version 1.0 of th
206
207 * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The V
208 supported, as defined by version 1.0 of th
209
210 * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zi
211 supported as defined in the RISC-V ISA
212 58220614a5f ("Zimop is ratified/1.0").
213
214 * :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca
215 extensions for code size reduction, as
216 ("Zcf doesn't exist on RV64 as it conta
217 riscv-code-size-reduction.
218
219 * :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb
220 extensions for code size reduction, as
221 ("Zcf doesn't exist on RV64 as it conta
222 riscv-code-size-reduction.
223
224 * :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd
225 extensions for code size reduction, as
226 ("Zcf doesn't exist on RV64 as it conta
227 riscv-code-size-reduction.
228
229 * :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf
230 extensions for code size reduction, as
231 ("Zcf doesn't exist on RV64 as it conta
232 riscv-code-size-reduction.
233
234 * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zc
235 supported as defined in the RISC-V ISA
236 c732a4f39a4 ("Zcmop is ratified/1.0").
237
238 * :c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Za
239 ratified in commit 98918c844281 ("Merge
240 riscv/zawrs") of riscv-isa-manual.
241
242 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Depr
243 :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SC
244 mistakenly classified as a bitmask rather
245
246 * :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALA
247 the performance of misaligned scalar native
248 of processors.
249
250 * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_
251 misaligned scalar accesses is unknown.
252
253 * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_
254 accesses are emulated via software, either
255 accesses are always extremely slow.
256
257 * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_
258 word sized accesses are slower than the eq
259 accesses. Misaligned accesses may be suppo
260 trapped and emulated by software.
261
262 * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_
263 word sized accesses are faster than the eq
264 accesses.
265
266 * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_
267 accesses are not supported at all and will
268 fault.
269
270 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZ
271 represents the size of the Zicboz block in b
272
273 * :c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADD
274 represent the highest userspace virtual addr
275
276 * :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`:
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