1 .. SPDX-License-Identifier: GPL-2.0
2
3 RISC-V Linux User ABI
4 =====================
5
6 ISA string ordering in /proc/cpuinfo
7 ------------------------------------
8
9 The canonical order of ISA extension names in
10 chapter 27 of the unprivileged specification.
11 The specification uses vague wording, such as
12 so for our purposes the following rules apply:
13
14 #. Single-letter extensions come first, in can
15 The canonical order is "IMAFDQLCBKJTPVH".
16
17 #. All multi-letter extensions will be separat
18 underscore.
19
20 #. Additional standard extensions (starting wi
21 single-letter extensions and before any hig
22
23 #. For additional standard extensions, the fir
24 conventionally indicates the most closely r
25 extension category. If multiple 'Z' extensi
26 ordered first by category, in canonical ord
27 alphabetically within a category.
28
29 #. Standard supervisor-level extensions (start
30 after standard unprivileged extensions. If
31 extensions are listed, they will be ordered
32
33 #. Standard machine-level extensions (starting
34 after any lower-privileged, standard extens
35 extensions are listed, they will be ordered
36
37 #. Non-standard extensions (starting with 'X')
38 extensions. If multiple non-standard extens
39 ordered alphabetically.
40
41 An example string following the order is::
42
43 rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmba
44
45 "isa" and "hart isa" lines in /proc/cpuinfo
46 -------------------------------------------
47
48 The "isa" line in /proc/cpuinfo describes the
49 RISC-V ISA extensions recognized by the kernel
50 "hart isa" line, in contrast, describes the se
51 kernel on the particular hart being described,
52 be present on all harts in the system.
53
54 In both lines, the presence of an extension gu
55 has the described capability. Additional kerne
56 required before an extension's capability is f
57 Similarly, for S-mode extensions, presence in
58 guarantee that the kernel is taking advantage
59 feature will be visible in guest VMs managed b
60
61 Inversely, the absence of an extension in thes
62 the hardware does not support that feature. Th
63 the extension, or may have deliberately remove
64
65 Misaligned accesses
66 -------------------
67
68 Misaligned scalar accesses are supported in us
69 poorly. Misaligned vector accesses are only s
70 is supported.
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