1 .. SPDX-License-Identifier: GPL-2.0
2
3 ==============
4 Kernel Entries
5 ==============
6
7 This file documents some of the kernel entries
8 arch/x86/entry/entry_64.S. A lot of this expl
9 an email from Ingo Molnar:
10
11 https://lore.kernel.org/r/20110529191055.GC983
12
13 The x86 architecture has quite a few different
14 kernel code. Most of these entry points are r
15 arch/x86/kernel/traps.c and implemented in arc
16 for 64-bit, arch/x86/entry/entry_32.S for 32-b
17 arch/x86/entry/entry_64_compat.S which impleme
18 syscall entry points and thus provides for 32-
19 ability to execute syscalls when running on 64
20
21 The IDT vector assignments are listed in arch/
22
23 Some of these entries are:
24
25 - system_call: syscall instruction from 64-bi
26
27 - entry_INT80_compat: int 0x80 from 32-bit or
28 either way.
29
30 - entry_INT80_compat, ia32_sysenter: syscall
31 code
32
33 - interrupt: An array of entries. Every IDT
34 explicitly point somewhere else gets set to
35 value in interrupts. These point to a whol
36 magically-generated functions that make the
37 with the interrupt number as a parameter.
38
39 - APIC interrupts: Various special-purpose in
40 like TLB shootdown.
41
42 - Architecturally-defined exceptions like div
43
44 There are a few complexities here. The differ
45 have different calling conventions. The sysca
46 instructions have their own peculiar calling c
47 the IDT entries push an error code onto the st
48 IDT entries using the IST alternative stack me
49 magic to get the stack frames right. (You can
50 documentation in the AMD APM, Volume 2, Chapte
51 Volume 3, Chapter 6.)
52
53 Dealing with the swapgs instruction is especia
54 toggles whether gs is the kernel gs or the use
55 instruction is rather fragile: it must nest pe
56 single depth, it should only be used if enteri
57 kernel mode and then when returning to user-sp
58 so. If we mess that up even slightly, we crash
59
60 So when we have a secondary entry, already in
61 not* use SWAPGS blindly - nor must we forget d
62 not switched/swapped yet.
63
64 Now, there's a secondary complication: there's
65 which mode the CPU is in and an expensive way.
66
67 The cheap way is to pick this info off the ent
68 stack, from the CS of the ptregs area of the k
69
70 xorl %ebx,%ebx
71 testl $3,CS+8(%rsp)
72 je error_kernelspace
73 SWAPGS
74
75 The expensive (paranoid) way is to read back t
76 (which is what SWAPGS modifies)::
77
78 movl $1,%ebx
79 movl $MSR_GS_BASE,%ecx
80 rdmsr
81 testl %edx,%edx
82 js 1f /* negative -> in kernel */
83 SWAPGS
84 xorl %ebx,%ebx
85 1: ret
86
87 If we are at an interrupt or user-trap/gate-al
88 use the faster check: the stack will be a reli
89 whether SWAPGS was already done: if we see tha
90 entry interrupting kernel mode execution, then
91 base has already been switched. If it says tha
92 user-space execution then we must do the SWAPG
93
94 But if we are in an NMI/MCE/DEBUG/whatever sup
95 which might have triggered right after a norma
96 stack but before we executed SWAPGS, then the
97 for GS is the slower method: the RDMSR.
98
99 Therefore, super-atomic entries (except NMI, w
100 must use idtentry with paranoid=1 to handle gs
101 triggers three main behavior changes:
102
103 - Interrupt entry will use the slower gsbase
104 - Interrupt entry from user mode will switch
105 - Interrupt exit to kernel mode will not atte
106
107 We try to only use IST entries and the paranoi
108 that absolutely need the more expensive check
109 generate all 'normal' entry points with the re
110 variant.
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