1 =============================
2 MMUv3 initialization sequence
3 =============================
4
5 The code in the initialize_mmu macro sets up M
6 identically to MMUv2 fixed memory mapping. Dep
7 CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX sy
8 located in addresses it was linked for (symbol
9 (symbol defined), so it needs to be position-i
10
11 The code has the following assumptions:
12
13 - This code fragment is run only on an MMU v
14 - TLBs are in their reset state.
15 - ITLBCFG and DTLBCFG are zero (reset state)
16 - RASID is 0x04030201 (reset state).
17 - PS.RING is zero (reset state).
18 - LITBASE is zero (reset state, PC-relative
19
20 TLB setup proceeds along the following steps.
21
22 Legend:
23
24 - VA = virtual address (two upper nibbles
25 - PA = physical address (two upper nibbles
26 - pc = physical range that contains this c
27
28 After step 2, we jump to virtual address in th
29 or 0x00000000..0x1fffffff, depending on whethe
30 0x40000000 or above. That address corresponds
31 in this code. After step 4, we jump to intende
32 The scheme below assumes that the kernel is lo
33
34 ====== ===== ===== ===== ===== ====== ==
35 - Step0 Step1 Step2 Step3 St
36
37 VA PA PA PA PA VA
38 ====== ===== ===== ===== ===== ====== ==
39 E0..FF -> E0 -> E0 -> E0 F0..FF ->
40 C0..DF -> C0 -> C0 -> C0 E0..EF ->
41 A0..BF -> A0 -> A0 -> A0 D8..DF ->
42 80..9F -> 80 -> 80 -> 80 D0..D7 ->
43 60..7F -> 60 -> 60 -> 60
44 40..5F -> 40 -> pc -> pc 40..5F ->
45 20..3F -> 20 -> 20 -> 20
46 00..1F -> 00 -> 00 -> 00
47 ====== ===== ===== ===== ===== ====== ==
48
49 The default location of IO peripherals is abov
50 using a "ranges" property in a device tree sim
51 Specification, section 4.5 for details on the
52 simple-bus nodes. The following limitations ap
53
54 1. Only top level simple-bus nodes are conside
55
56 2. Only one (first) simple-bus node is conside
57
58 3. Empty "ranges" properties are not supported
59
60 4. Only the first triplet in the "ranges" prop
61
62 5. The parent-bus-address value is rounded dow
63
64 6. The IO area covers the entire 256MB segment
65 "ranges" triplet length field is ignored
66
67
68 MMUv3 address space layouts.
69 ============================
70
71 Default MMUv2-compatible layout::
72
73 Symbol
74 +------------------+
75 | Userspace |
76 +------------------+
77 +------------------+
78 | Page table | XCHAL_PAGE_TABLE_VADDR
79 +------------------+
80 | KASAN shadow map | KASAN_SHADOW_START
81 +------------------+
82 +------------------+
83 | VMALLOC area | VMALLOC_START
84 +------------------+ VMALLOC_END
85 +------------------+
86 | Cache aliasing | TLBTEMP_BASE_1
87 | remap area 1 |
88 +------------------+
89 | Cache aliasing | TLBTEMP_BASE_2
90 | remap area 2 |
91 +------------------+
92 +------------------+
93 | KMAP area | PKMAP_BASE
94 | |
95 | |
96 | |
97 +------------------+
98 | Atomic KMAP area | FIXADDR_START
99 | |
100 | |
101 | |
102 +------------------+ FIXADDR_TOP
103 +------------------+
104 | Cached KSEG | XCHAL_KSEG_CACHED_VADD
105 +------------------+
106 | Uncached KSEG | XCHAL_KSEG_BYPASS_VADD
107 +------------------+
108 | Cached KIO | XCHAL_KIO_CACHED_VADDR
109 +------------------+
110 | Uncached KIO | XCHAL_KIO_BYPASS_VADDR
111 +------------------+
112
113
114 256MB cached + 256MB uncached layout::
115
116 Symbol
117 +------------------+
118 | Userspace |
119 +------------------+
120 +------------------+
121 | Page table | XCHAL_PAGE_TABLE_VADDR
122 +------------------+
123 | KASAN shadow map | KASAN_SHADOW_START
124 +------------------+
125 +------------------+
126 | VMALLOC area | VMALLOC_START
127 +------------------+ VMALLOC_END
128 +------------------+
129 | Cache aliasing | TLBTEMP_BASE_1
130 | remap area 1 |
131 +------------------+
132 | Cache aliasing | TLBTEMP_BASE_2
133 | remap area 2 |
134 +------------------+
135 +------------------+
136 | KMAP area | PKMAP_BASE
137 | |
138 | |
139 | |
140 +------------------+
141 | Atomic KMAP area | FIXADDR_START
142 | |
143 | |
144 | |
145 +------------------+ FIXADDR_TOP
146 +------------------+
147 | Cached KSEG | XCHAL_KSEG_CACHED_VADD
148 +------------------+
149 | Uncached KSEG | XCHAL_KSEG_BYPASS_VADD
150 +------------------+
151 +------------------+
152 | Cached KIO | XCHAL_KIO_CACHED_VADDR
153 +------------------+
154 | Uncached KIO | XCHAL_KIO_BYPASS_VADDR
155 +------------------+
156
157
158 512MB cached + 512MB uncached layout::
159
160 Symbol
161 +------------------+
162 | Userspace |
163 +------------------+
164 +------------------+
165 | Page table | XCHAL_PAGE_TABLE_VADDR
166 +------------------+
167 | KASAN shadow map | KASAN_SHADOW_START
168 +------------------+
169 +------------------+
170 | VMALLOC area | VMALLOC_START
171 +------------------+ VMALLOC_END
172 +------------------+
173 | Cache aliasing | TLBTEMP_BASE_1
174 | remap area 1 |
175 +------------------+
176 | Cache aliasing | TLBTEMP_BASE_2
177 | remap area 2 |
178 +------------------+
179 +------------------+
180 | KMAP area | PKMAP_BASE
181 | |
182 | |
183 | |
184 +------------------+
185 | Atomic KMAP area | FIXADDR_START
186 | |
187 | |
188 | |
189 +------------------+ FIXADDR_TOP
190 +------------------+
191 | Cached KSEG | XCHAL_KSEG_CACHED_VADD
192 +------------------+
193 | Uncached KSEG | XCHAL_KSEG_BYPASS_VADD
194 +------------------+
195 | Cached KIO | XCHAL_KIO_CACHED_VADDR
196 +------------------+
197 | Uncached KIO | XCHAL_KIO_BYPASS_VADDR
198 +------------------+
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