1 ============================================== 1 ========================================================
2 Secondary CPU enable-method "al,alpine-smp" bi 2 Secondary CPU enable-method "al,alpine-smp" binding
3 ============================================== 3 ========================================================
4 4
5 This document describes the "al,alpine-smp" me 5 This document describes the "al,alpine-smp" method for
6 enabling secondary CPUs. To apply to all CPUs, 6 enabling secondary CPUs. To apply to all CPUs, a single
7 "al,alpine-smp" enable method should be define 7 "al,alpine-smp" enable method should be defined in the
8 "cpus" node. 8 "cpus" node.
9 9
10 Enable method name: "al,alpine-smp" 10 Enable method name: "al,alpine-smp"
11 Compatible machines: "al,alpine" 11 Compatible machines: "al,alpine"
12 Compatible CPUs: "arm,cortex-a15" 12 Compatible CPUs: "arm,cortex-a15"
13 Related properties: (none) 13 Related properties: (none)
14 14
15 Note: 15 Note:
16 This enable method requires valid nodes compat 16 This enable method requires valid nodes compatible with
17 "al,alpine-cpu-resume" and "al,alpine-nb-servi 17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
18 18
19 19
20 * Alpine CPU resume registers 20 * Alpine CPU resume registers
21 21
22 The CPU resume register are used to define req 22 The CPU resume register are used to define required resume address after
23 reset. 23 reset.
24 24
25 Properties: 25 Properties:
26 - compatible : Should contain "al,alpine-cpu-r 26 - compatible : Should contain "al,alpine-cpu-resume".
27 - reg : Offset and length of the register set 27 - reg : Offset and length of the register set for the device
28 28
29 29
30 Example: 30 Example:
31 31
32 cpus { 32 cpus {
33 #address-cells = <1>; 33 #address-cells = <1>;
34 #size-cells = <0>; 34 #size-cells = <0>;
35 enable-method = "al,alpine-smp"; 35 enable-method = "al,alpine-smp";
36 36
37 cpu@0 { 37 cpu@0 {
38 compatible = "arm,cortex-a15"; 38 compatible = "arm,cortex-a15";
39 device_type = "cpu"; 39 device_type = "cpu";
40 reg = <0>; 40 reg = <0>;
41 }; 41 };
42 42
43 cpu@1 { 43 cpu@1 {
44 compatible = "arm,cortex-a15"; 44 compatible = "arm,cortex-a15";
45 device_type = "cpu"; 45 device_type = "cpu";
46 reg = <1>; 46 reg = <1>;
47 }; 47 };
48 48
49 cpu@2 { 49 cpu@2 {
50 compatible = "arm,cortex-a15"; 50 compatible = "arm,cortex-a15";
51 device_type = "cpu"; 51 device_type = "cpu";
52 reg = <2>; 52 reg = <2>;
53 }; 53 };
54 54
55 cpu@3 { 55 cpu@3 {
56 compatible = "arm,cortex-a15"; 56 compatible = "arm,cortex-a15";
57 device_type = "cpu"; 57 device_type = "cpu";
58 reg = <3>; 58 reg = <3>;
59 }; 59 };
60 }; 60 };
61 61
62 cpu_resume { 62 cpu_resume {
63 compatible = "al,alpine-cpu-resume"; 63 compatible = "al,alpine-cpu-resume";
64 reg = <0xfbff5ed0 0x30>; 64 reg = <0xfbff5ed0 0x30>;
65 }; 65 };
66 66
67 nb_service { 67 nb_service {
68 compatible = "al,alpine-sysfabric-serv 68 compatible = "al,alpine-sysfabric-service", "syscon";
69 reg = <0xfb070000 0x10000>; 69 reg = <0xfb070000 0x10000>;
70 }; 70 };
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