1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/arm/cpus.ya 4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ARM CPUs 7 title: ARM CPUs
8 8
9 maintainers: 9 maintainers:
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.co 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 11
12 description: |+ 12 description: |+
13 The device tree allows to describe the layou 13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a nu 14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu. 15 defining properties for every cpu.
16 16
17 Bindings for CPU nodes follow the Devicetree 17 Bindings for CPU nodes follow the Devicetree Specification, available from:
18 18
19 https://www.devicetree.org/specifications/ 19 https://www.devicetree.org/specifications/
20 20
21 with updates for 32-bit and 64-bit ARM syste 21 with updates for 32-bit and 64-bit ARM systems provided in this document.
22 22
23 ================================ 23 ================================
24 Convention used in this document 24 Convention used in this document
25 ================================ 25 ================================
26 26
27 This document follows the conventions descri 27 This document follows the conventions described in the Devicetree
28 Specification, with the addition: 28 Specification, with the addition:
29 29
30 - square brackets define bitfields, eg reg[7 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down 31 the reg property contained in bits 7 down to 0
32 32
33 ===================================== 33 =====================================
34 cpus and cpu node bindings definition 34 cpus and cpu node bindings definition
35 ===================================== 35 =====================================
36 36
37 The ARM architecture, in accordance with the 37 The ARM architecture, in accordance with the Devicetree Specification,
38 requires the cpus and cpu nodes to be presen 38 requires the cpus and cpu nodes to be present and contain the properties
39 described below. 39 described below.
40 40
41 properties: 41 properties:
42 reg: 42 reg:
43 maxItems: 1 43 maxItems: 1
44 description: | 44 description: |
45 Usage and definition depend on ARM archi 45 Usage and definition depend on ARM architecture version and
46 configuration: 46 configuration:
47 47
48 On uniprocessor ARM architectures previo 48 On uniprocessor ARM architectures previous to v7
49 this property is required and must be se 49 this property is required and must be set to 0.
50 50
51 On ARM 11 MPcore based systems this prop 51 On ARM 11 MPcore based systems this property is
52 required and matches the CPUID[11:0] r 52 required and matches the CPUID[11:0] register bits.
53 53
54 Bits [11:0] in the reg cell must be se 54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register. 55 bits [11:0] in CPU ID register.
56 56
57 All other bits in the reg cell must be 57 All other bits in the reg cell must be set to 0.
58 58
59 On 32-bit ARM v7 or later systems this p 59 On 32-bit ARM v7 or later systems this property is
60 required and matches the CPU MPIDR[23: 60 required and matches the CPU MPIDR[23:0] register
61 bits. 61 bits.
62 62
63 Bits [23:0] in the reg cell must be se 63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR. 64 bits [23:0] in MPIDR.
65 65
66 All other bits in the reg cell must be 66 All other bits in the reg cell must be set to 0.
67 67
68 On ARM v8 64-bit systems this property i 68 On ARM v8 64-bit systems this property is required
69 and matches the MPIDR_EL1 register aff 69 and matches the MPIDR_EL1 register affinity bits.
70 70
71 * If cpus node's #address-cells proper 71 * If cpus node's #address-cells property is set to 2
72 72
73 The first reg cell bits [7:0] must b 73 The first reg cell bits [7:0] must be set to
74 bits [39:32] of MPIDR_EL1. 74 bits [39:32] of MPIDR_EL1.
75 75
76 The second reg cell bits [23:0] must 76 The second reg cell bits [23:0] must be set to
77 bits [23:0] of MPIDR_EL1. 77 bits [23:0] of MPIDR_EL1.
78 78
79 * If cpus node's #address-cells proper 79 * If cpus node's #address-cells property is set to 1
80 80
81 The reg cell bits [23:0] must be set 81 The reg cell bits [23:0] must be set to bits [23:0]
82 of MPIDR_EL1. 82 of MPIDR_EL1.
83 83
84 All other bits in the reg cells must be 84 All other bits in the reg cells must be set to 0.
85 85
86 compatible: 86 compatible:
87 enum: 87 enum:
88 - apple,avalanche 88 - apple,avalanche
89 - apple,blizzard 89 - apple,blizzard
90 - apple,icestorm 90 - apple,icestorm
91 - apple,firestorm 91 - apple,firestorm
92 - arm,arm710t 92 - arm,arm710t
93 - arm,arm720t 93 - arm,arm720t
94 - arm,arm740t 94 - arm,arm740t
95 - arm,arm7ej-s 95 - arm,arm7ej-s
96 - arm,arm7tdmi 96 - arm,arm7tdmi
97 - arm,arm7tdmi-s 97 - arm,arm7tdmi-s
98 - arm,arm9es 98 - arm,arm9es
99 - arm,arm9ej-s 99 - arm,arm9ej-s
100 - arm,arm920t 100 - arm,arm920t
101 - arm,arm922t 101 - arm,arm922t
102 - arm,arm925 102 - arm,arm925
103 - arm,arm926e-s 103 - arm,arm926e-s
104 - arm,arm926ej-s 104 - arm,arm926ej-s
105 - arm,arm940t 105 - arm,arm940t
106 - arm,arm946e-s 106 - arm,arm946e-s
107 - arm,arm966e-s 107 - arm,arm966e-s
108 - arm,arm968e-s 108 - arm,arm968e-s
109 - arm,arm9tdmi 109 - arm,arm9tdmi
110 - arm,arm1020e 110 - arm,arm1020e
111 - arm,arm1020t 111 - arm,arm1020t
112 - arm,arm1022e 112 - arm,arm1022e
113 - arm,arm1026ej-s 113 - arm,arm1026ej-s
114 - arm,arm1136j-s 114 - arm,arm1136j-s
115 - arm,arm1136jf-s 115 - arm,arm1136jf-s
116 - arm,arm1156t2-s 116 - arm,arm1156t2-s
117 - arm,arm1156t2f-s 117 - arm,arm1156t2f-s
118 - arm,arm1176jzf 118 - arm,arm1176jzf
119 - arm,arm1176jz-s 119 - arm,arm1176jz-s
120 - arm,arm1176jzf-s 120 - arm,arm1176jzf-s
121 - arm,arm11mpcore 121 - arm,arm11mpcore
122 - arm,armv8 # Only for s/w models 122 - arm,armv8 # Only for s/w models
123 - arm,cortex-a5 123 - arm,cortex-a5
124 - arm,cortex-a7 124 - arm,cortex-a7
125 - arm,cortex-a8 125 - arm,cortex-a8
126 - arm,cortex-a9 126 - arm,cortex-a9
127 - arm,cortex-a12 127 - arm,cortex-a12
128 - arm,cortex-a15 128 - arm,cortex-a15
129 - arm,cortex-a17 129 - arm,cortex-a17
130 - arm,cortex-a32 130 - arm,cortex-a32
131 - arm,cortex-a34 131 - arm,cortex-a34
132 - arm,cortex-a35 132 - arm,cortex-a35
133 - arm,cortex-a53 133 - arm,cortex-a53
134 - arm,cortex-a55 134 - arm,cortex-a55
135 - arm,cortex-a57 135 - arm,cortex-a57
136 - arm,cortex-a65 136 - arm,cortex-a65
137 - arm,cortex-a72 137 - arm,cortex-a72
138 - arm,cortex-a73 138 - arm,cortex-a73
139 - arm,cortex-a75 139 - arm,cortex-a75
140 - arm,cortex-a76 140 - arm,cortex-a76
141 - arm,cortex-a77 141 - arm,cortex-a77
142 - arm,cortex-a78 142 - arm,cortex-a78
143 - arm,cortex-a78ae 143 - arm,cortex-a78ae
144 - arm,cortex-a78c 144 - arm,cortex-a78c
145 - arm,cortex-a510 145 - arm,cortex-a510
146 - arm,cortex-a520 146 - arm,cortex-a520
147 - arm,cortex-a710 147 - arm,cortex-a710
148 - arm,cortex-a715 148 - arm,cortex-a715
149 - arm,cortex-a720 149 - arm,cortex-a720
150 - arm,cortex-a725 150 - arm,cortex-a725
151 - arm,cortex-m0 151 - arm,cortex-m0
152 - arm,cortex-m0+ 152 - arm,cortex-m0+
153 - arm,cortex-m1 153 - arm,cortex-m1
154 - arm,cortex-m3 154 - arm,cortex-m3
155 - arm,cortex-m4 155 - arm,cortex-m4
156 - arm,cortex-r4 156 - arm,cortex-r4
157 - arm,cortex-r5 157 - arm,cortex-r5
158 - arm,cortex-r7 158 - arm,cortex-r7
159 - arm,cortex-r52 159 - arm,cortex-r52
160 - arm,cortex-x1 160 - arm,cortex-x1
161 - arm,cortex-x1c 161 - arm,cortex-x1c
162 - arm,cortex-x2 162 - arm,cortex-x2
163 - arm,cortex-x3 163 - arm,cortex-x3
164 - arm,cortex-x4 164 - arm,cortex-x4
165 - arm,cortex-x925 165 - arm,cortex-x925
166 - arm,neoverse-e1 166 - arm,neoverse-e1
167 - arm,neoverse-n1 167 - arm,neoverse-n1
168 - arm,neoverse-n2 168 - arm,neoverse-n2
169 - arm,neoverse-n3 169 - arm,neoverse-n3
170 - arm,neoverse-v1 170 - arm,neoverse-v1
171 - arm,neoverse-v2 171 - arm,neoverse-v2
172 - arm,neoverse-v3 172 - arm,neoverse-v3
173 - arm,neoverse-v3ae 173 - arm,neoverse-v3ae
174 - brcm,brahma-b15 174 - brcm,brahma-b15
175 - brcm,brahma-b53 175 - brcm,brahma-b53
176 - brcm,vulcan 176 - brcm,vulcan
177 - cavium,thunder 177 - cavium,thunder
178 - cavium,thunder2 178 - cavium,thunder2
179 - faraday,fa526 179 - faraday,fa526
180 - intel,sa110 180 - intel,sa110
181 - intel,sa1100 181 - intel,sa1100
182 - marvell,feroceon 182 - marvell,feroceon
183 - marvell,mohawk 183 - marvell,mohawk
184 - marvell,pj4a 184 - marvell,pj4a
185 - marvell,pj4b 185 - marvell,pj4b
186 - marvell,sheeva-v5 186 - marvell,sheeva-v5
187 - marvell,sheeva-v7 187 - marvell,sheeva-v7
188 - nvidia,tegra132-denver 188 - nvidia,tegra132-denver
189 - nvidia,tegra186-denver 189 - nvidia,tegra186-denver
190 - nvidia,tegra194-carmel 190 - nvidia,tegra194-carmel
191 - qcom,krait 191 - qcom,krait
192 - qcom,kryo 192 - qcom,kryo
193 - qcom,kryo240 193 - qcom,kryo240
194 - qcom,kryo250 194 - qcom,kryo250
195 - qcom,kryo260 195 - qcom,kryo260
196 - qcom,kryo280 196 - qcom,kryo280
197 - qcom,kryo360 197 - qcom,kryo360
198 - qcom,kryo385 198 - qcom,kryo385
199 - qcom,kryo465 199 - qcom,kryo465
200 - qcom,kryo468 200 - qcom,kryo468
201 - qcom,kryo485 201 - qcom,kryo485
202 - qcom,kryo560 202 - qcom,kryo560
203 - qcom,kryo570 203 - qcom,kryo570
204 - qcom,kryo660 204 - qcom,kryo660
205 - qcom,kryo685 205 - qcom,kryo685
206 - qcom,kryo780 206 - qcom,kryo780
207 - qcom,oryon 207 - qcom,oryon
208 - qcom,scorpion 208 - qcom,scorpion
209 209
210 enable-method: 210 enable-method:
211 $ref: /schemas/types.yaml#/definitions/str 211 $ref: /schemas/types.yaml#/definitions/string
212 oneOf: 212 oneOf:
213 # On ARM v8 64-bit this property is requ 213 # On ARM v8 64-bit this property is required
214 - enum: 214 - enum:
215 - psci 215 - psci
216 - spin-table 216 - spin-table
217 # On ARM 32-bit systems this property is 217 # On ARM 32-bit systems this property is optional
218 - enum: 218 - enum:
219 - actions,s500-smp 219 - actions,s500-smp
220 - allwinner,sun6i-a31 220 - allwinner,sun6i-a31
221 - allwinner,sun8i-a23 221 - allwinner,sun8i-a23
222 - allwinner,sun9i-a80-smp 222 - allwinner,sun9i-a80-smp
223 - allwinner,sun8i-a83t-smp 223 - allwinner,sun8i-a83t-smp
224 - amlogic,meson8-smp 224 - amlogic,meson8-smp
225 - amlogic,meson8b-smp 225 - amlogic,meson8b-smp
226 - arm,realview-smp 226 - arm,realview-smp
227 - aspeed,ast2600-smp 227 - aspeed,ast2600-smp
228 - brcm,bcm11351-cpu-method 228 - brcm,bcm11351-cpu-method
229 - brcm,bcm23550 229 - brcm,bcm23550
230 - brcm,bcm2836-smp 230 - brcm,bcm2836-smp
231 - brcm,bcm63138 231 - brcm,bcm63138
232 - brcm,bcm-nsp-smp 232 - brcm,bcm-nsp-smp
233 - brcm,brahma-b15 233 - brcm,brahma-b15
234 - marvell,armada-375-smp 234 - marvell,armada-375-smp
235 - marvell,armada-380-smp 235 - marvell,armada-380-smp
236 - marvell,armada-390-smp 236 - marvell,armada-390-smp
237 - marvell,armada-xp-smp 237 - marvell,armada-xp-smp
238 - marvell,98dx3236-smp 238 - marvell,98dx3236-smp
239 - marvell,mmp3-smp 239 - marvell,mmp3-smp
240 - mediatek,mt6589-smp 240 - mediatek,mt6589-smp
241 - mediatek,mt81xx-tz-smp 241 - mediatek,mt81xx-tz-smp
242 - qcom,gcc-msm8660 242 - qcom,gcc-msm8660
243 - qcom,kpss-acc-v1 243 - qcom,kpss-acc-v1
244 - qcom,kpss-acc-v2 244 - qcom,kpss-acc-v2
245 - qcom,msm8226-smp 245 - qcom,msm8226-smp
246 - qcom,msm8909-smp 246 - qcom,msm8909-smp
247 # Only valid on ARM 32-bit, see abov 247 # Only valid on ARM 32-bit, see above for ARM v8 64-bit
248 - qcom,msm8916-smp 248 - qcom,msm8916-smp
249 - renesas,apmu 249 - renesas,apmu
250 - renesas,r9a06g032-smp 250 - renesas,r9a06g032-smp
251 - rockchip,rk3036-smp 251 - rockchip,rk3036-smp
252 - rockchip,rk3066-smp 252 - rockchip,rk3066-smp
253 - socionext,milbeaut-m10v-smp 253 - socionext,milbeaut-m10v-smp
254 - ste,dbx500-smp 254 - ste,dbx500-smp
255 - ti,am3352 255 - ti,am3352
256 - ti,am4372 256 - ti,am4372
257 257
258 cpu-release-addr: 258 cpu-release-addr:
259 oneOf: 259 oneOf:
260 - $ref: /schemas/types.yaml#/definitions 260 - $ref: /schemas/types.yaml#/definitions/uint32
261 - $ref: /schemas/types.yaml#/definitions 261 - $ref: /schemas/types.yaml#/definitions/uint64
262 description: 262 description:
263 The DT specification defines this as 64- 263 The DT specification defines this as 64-bit always, but some 32-bit Arm
264 systems have used a 32-bit value which m 264 systems have used a 32-bit value which must be supported.
265 Required for systems that have an "enabl 265 Required for systems that have an "enable-method"
266 property value of "spin-table". 266 property value of "spin-table".
267 267
268 cpu-idle-states: 268 cpu-idle-states:
269 $ref: /schemas/types.yaml#/definitions/pha 269 $ref: /schemas/types.yaml#/definitions/phandle-array
270 items: 270 items:
271 maxItems: 1 271 maxItems: 1
272 description: | 272 description: |
273 List of phandles to idle state nodes sup 273 List of phandles to idle state nodes supported
274 by this cpu (see ./idle-states.yaml). 274 by this cpu (see ./idle-states.yaml).
275 275
276 capacity-dmips-mhz: 276 capacity-dmips-mhz:
277 description: 277 description:
278 u32 value representing CPU capacity (see 278 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
279 DMIPS/MHz, relative to highest capacity- 279 DMIPS/MHz, relative to highest capacity-dmips-mhz
280 in the system. 280 in the system.
281 281
282 cci-control-port: true 282 cci-control-port: true
283 283
284 dynamic-power-coefficient: 284 dynamic-power-coefficient:
285 $ref: /schemas/types.yaml#/definitions/uin 285 $ref: /schemas/types.yaml#/definitions/uint32
286 description: 286 description:
287 A u32 value that represents the running 287 A u32 value that represents the running time dynamic
288 power coefficient in units of uW/MHz/V^2 288 power coefficient in units of uW/MHz/V^2. The
289 coefficient can either be calculated fro 289 coefficient can either be calculated from power
290 measurements or derived by analysis. 290 measurements or derived by analysis.
291 291
292 The dynamic power consumption of the CPU 292 The dynamic power consumption of the CPU is
293 proportional to the square of the Voltag 293 proportional to the square of the Voltage (V) and
294 the clock frequency (f). The coefficient 294 the clock frequency (f). The coefficient is used to
295 calculate the dynamic power as below - 295 calculate the dynamic power as below -
296 296
297 Pdyn = dynamic-power-coefficient * V^2 * 297 Pdyn = dynamic-power-coefficient * V^2 * f
298 298
299 where voltage is in V, frequency is in M 299 where voltage is in V, frequency is in MHz.
300 300
301 performance-domains: 301 performance-domains:
302 maxItems: 1 302 maxItems: 1
303 description: 303 description:
304 List of phandles and performance domain 304 List of phandles and performance domain specifiers, as defined by
305 bindings of the performance domain provi 305 bindings of the performance domain provider. See also
306 dvfs/performance-domain.yaml. 306 dvfs/performance-domain.yaml.
307 307
308 power-domains: 308 power-domains:
309 description: 309 description:
310 List of phandles and PM domain specifier 310 List of phandles and PM domain specifiers, as defined by bindings of the
311 PM domain provider (see also ../power_do 311 PM domain provider (see also ../power_domain.txt).
312 312
313 power-domain-names: 313 power-domain-names:
314 description: 314 description:
315 A list of power domain name strings sort 315 A list of power domain name strings sorted in the same order as the
316 power-domains property. 316 power-domains property.
317 317
318 For PSCI based platforms, the name corre 318 For PSCI based platforms, the name corresponding to the index of the PSCI
319 PM domain provider, must be "psci". For 319 PM domain provider, must be "psci". For SCMI based platforms, the name
320 corresponding to the index of an SCMI pe 320 corresponding to the index of an SCMI performance domain provider, must be
321 "perf". 321 "perf".
322 322
323 qcom,saw: 323 qcom,saw:
324 $ref: /schemas/types.yaml#/definitions/pha 324 $ref: /schemas/types.yaml#/definitions/phandle
325 description: | 325 description: |
326 Specifies the SAW* node associated with 326 Specifies the SAW* node associated with this CPU.
327 327
328 Required for systems that have an "enabl 328 Required for systems that have an "enable-method" property
329 value of "qcom,kpss-acc-v1" or "qcom,kps 329 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
330 330
331 * arm/msm/qcom,saw2.txt 331 * arm/msm/qcom,saw2.txt
332 332
333 qcom,acc: 333 qcom,acc:
334 $ref: /schemas/types.yaml#/definitions/pha 334 $ref: /schemas/types.yaml#/definitions/phandle
335 description: | 335 description: |
336 Specifies the ACC* node associated with 336 Specifies the ACC* node associated with this CPU.
337 337
338 Required for systems that have an "enabl 338 Required for systems that have an "enable-method" property
339 value of "qcom,kpss-acc-v1", "qcom,kpss- 339 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
340 "qcom,msm8916-smp". 340 "qcom,msm8916-smp".
341 341
342 * arm/msm/qcom,kpss-acc.txt 342 * arm/msm/qcom,kpss-acc.txt
343 343
344 rockchip,pmu: 344 rockchip,pmu:
345 $ref: /schemas/types.yaml#/definitions/pha 345 $ref: /schemas/types.yaml#/definitions/phandle
346 description: | 346 description: |
347 Specifies the syscon node controlling th 347 Specifies the syscon node controlling the cpu core power domains.
348 348
349 Optional for systems that have an "enabl 349 Optional for systems that have an "enable-method"
350 property value of "rockchip,rk3066-smp" 350 property value of "rockchip,rk3066-smp"
351 While optional, it is the preferred way 351 While optional, it is the preferred way to get access to
352 the cpu-core power-domains. 352 the cpu-core power-domains.
353 353
354 secondary-boot-reg: 354 secondary-boot-reg:
355 $ref: /schemas/types.yaml#/definitions/uin 355 $ref: /schemas/types.yaml#/definitions/uint32
356 description: | 356 description: |
357 Required for systems that have an "enabl 357 Required for systems that have an "enable-method" property value of
358 "brcm,bcm11351-cpu-method", "brcm,bcm235 358 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
359 359
360 This includes the following SoCs: | 360 This includes the following SoCs: |
361 BCM11130, BCM11140, BCM11351, BCM28145, 361 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
362 BCM58522, BCM58525, BCM58535, BCM58622, 362 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
363 363
364 The secondary-boot-reg property is a u32 364 The secondary-boot-reg property is a u32 value that specifies the
365 physical address of the register used to 365 physical address of the register used to request the ROM holding pen
366 code release a secondary CPU. The value 366 code release a secondary CPU. The value written to the register is
367 formed by encoding the target CPU id int 367 formed by encoding the target CPU id into the low bits of the
368 physical start address it should jump to 368 physical start address it should jump to.
369 369
370 if: 370 if:
371 # If the enable-method property contains one 371 # If the enable-method property contains one of those values
372 properties: 372 properties:
373 enable-method: 373 enable-method:
374 contains: 374 contains:
375 enum: 375 enum:
376 - brcm,bcm11351-cpu-method 376 - brcm,bcm11351-cpu-method
377 - brcm,bcm23550 377 - brcm,bcm23550
378 - brcm,bcm-nsp-smp 378 - brcm,bcm-nsp-smp
379 # and if enable-method is present 379 # and if enable-method is present
380 required: 380 required:
381 - enable-method 381 - enable-method
382 382
383 then: 383 then:
384 required: 384 required:
385 - secondary-boot-reg 385 - secondary-boot-reg
386 386
387 required: 387 required:
388 - device_type 388 - device_type
389 - reg 389 - reg
390 - compatible 390 - compatible
391 391
392 dependencies: 392 dependencies:
393 rockchip,pmu: [enable-method] 393 rockchip,pmu: [enable-method]
394 394
395 additionalProperties: true 395 additionalProperties: true
396 396
397 examples: 397 examples:
398 - | 398 - |
399 cpus { 399 cpus {
400 #size-cells = <0>; 400 #size-cells = <0>;
401 #address-cells = <1>; 401 #address-cells = <1>;
402 402
403 cpu@0 { 403 cpu@0 {
404 device_type = "cpu"; 404 device_type = "cpu";
405 compatible = "arm,cortex-a15"; 405 compatible = "arm,cortex-a15";
406 reg = <0x0>; 406 reg = <0x0>;
407 }; 407 };
408 408
409 cpu@1 { 409 cpu@1 {
410 device_type = "cpu"; 410 device_type = "cpu";
411 compatible = "arm,cortex-a15"; 411 compatible = "arm,cortex-a15";
412 reg = <0x1>; 412 reg = <0x1>;
413 }; 413 };
414 414
415 cpu@100 { 415 cpu@100 {
416 device_type = "cpu"; 416 device_type = "cpu";
417 compatible = "arm,cortex-a7"; 417 compatible = "arm,cortex-a7";
418 reg = <0x100>; 418 reg = <0x100>;
419 }; 419 };
420 420
421 cpu@101 { 421 cpu@101 {
422 device_type = "cpu"; 422 device_type = "cpu";
423 compatible = "arm,cortex-a7"; 423 compatible = "arm,cortex-a7";
424 reg = <0x101>; 424 reg = <0x101>;
425 }; 425 };
426 }; 426 };
427 427
428 - | 428 - |
429 // Example 2 (Cortex-A8 uniprocessor 32-bi 429 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
430 cpus { 430 cpus {
431 #size-cells = <0>; 431 #size-cells = <0>;
432 #address-cells = <1>; 432 #address-cells = <1>;
433 433
434 cpu@0 { 434 cpu@0 {
435 device_type = "cpu"; 435 device_type = "cpu";
436 compatible = "arm,cortex-a8"; 436 compatible = "arm,cortex-a8";
437 reg = <0x0>; 437 reg = <0x0>;
438 }; 438 };
439 }; 439 };
440 440
441 - | 441 - |
442 // Example 3 (ARM 926EJ-S uniprocessor 32- 442 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
443 cpus { 443 cpus {
444 #size-cells = <0>; 444 #size-cells = <0>;
445 #address-cells = <1>; 445 #address-cells = <1>;
446 446
447 cpu@0 { 447 cpu@0 {
448 device_type = "cpu"; 448 device_type = "cpu";
449 compatible = "arm,arm926ej-s"; 449 compatible = "arm,arm926ej-s";
450 reg = <0x0>; 450 reg = <0x0>;
451 }; 451 };
452 }; 452 };
453 453
454 - | 454 - |
455 // Example 4 (ARM Cortex-A57 64-bit syste 455 // Example 4 (ARM Cortex-A57 64-bit system):
456 cpus { 456 cpus {
457 #size-cells = <0>; 457 #size-cells = <0>;
458 #address-cells = <2>; 458 #address-cells = <2>;
459 459
460 cpu@0 { 460 cpu@0 {
461 device_type = "cpu"; 461 device_type = "cpu";
462 compatible = "arm,cortex-a57"; 462 compatible = "arm,cortex-a57";
463 reg = <0x0 0x0>; 463 reg = <0x0 0x0>;
464 enable-method = "spin-table"; 464 enable-method = "spin-table";
465 cpu-release-addr = <0 0x20000000>; 465 cpu-release-addr = <0 0x20000000>;
466 }; 466 };
467 467
468 cpu@1 { 468 cpu@1 {
469 device_type = "cpu"; 469 device_type = "cpu";
470 compatible = "arm,cortex-a57"; 470 compatible = "arm,cortex-a57";
471 reg = <0x0 0x1>; 471 reg = <0x0 0x1>;
472 enable-method = "spin-table"; 472 enable-method = "spin-table";
473 cpu-release-addr = <0 0x20000000>; 473 cpu-release-addr = <0 0x20000000>;
474 }; 474 };
475 475
476 cpu@100 { 476 cpu@100 {
477 device_type = "cpu"; 477 device_type = "cpu";
478 compatible = "arm,cortex-a57"; 478 compatible = "arm,cortex-a57";
479 reg = <0x0 0x100>; 479 reg = <0x0 0x100>;
480 enable-method = "spin-table"; 480 enable-method = "spin-table";
481 cpu-release-addr = <0 0x20000000>; 481 cpu-release-addr = <0 0x20000000>;
482 }; 482 };
483 483
484 cpu@101 { 484 cpu@101 {
485 device_type = "cpu"; 485 device_type = "cpu";
486 compatible = "arm,cortex-a57"; 486 compatible = "arm,cortex-a57";
487 reg = <0x0 0x101>; 487 reg = <0x0 0x101>;
488 enable-method = "spin-table"; 488 enable-method = "spin-table";
489 cpu-release-addr = <0 0x20000000>; 489 cpu-release-addr = <0 0x20000000>;
490 }; 490 };
491 491
492 cpu@10000 { 492 cpu@10000 {
493 device_type = "cpu"; 493 device_type = "cpu";
494 compatible = "arm,cortex-a57"; 494 compatible = "arm,cortex-a57";
495 reg = <0x0 0x10000>; 495 reg = <0x0 0x10000>;
496 enable-method = "spin-table"; 496 enable-method = "spin-table";
497 cpu-release-addr = <0 0x20000000>; 497 cpu-release-addr = <0 0x20000000>;
498 }; 498 };
499 499
500 cpu@10001 { 500 cpu@10001 {
501 device_type = "cpu"; 501 device_type = "cpu";
502 compatible = "arm,cortex-a57"; 502 compatible = "arm,cortex-a57";
503 reg = <0x0 0x10001>; 503 reg = <0x0 0x10001>;
504 enable-method = "spin-table"; 504 enable-method = "spin-table";
505 cpu-release-addr = <0 0x20000000>; 505 cpu-release-addr = <0 0x20000000>;
506 }; 506 };
507 507
508 cpu@10100 { 508 cpu@10100 {
509 device_type = "cpu"; 509 device_type = "cpu";
510 compatible = "arm,cortex-a57"; 510 compatible = "arm,cortex-a57";
511 reg = <0x0 0x10100>; 511 reg = <0x0 0x10100>;
512 enable-method = "spin-table"; 512 enable-method = "spin-table";
513 cpu-release-addr = <0 0x20000000>; 513 cpu-release-addr = <0 0x20000000>;
514 }; 514 };
515 515
516 cpu@10101 { 516 cpu@10101 {
517 device_type = "cpu"; 517 device_type = "cpu";
518 compatible = "arm,cortex-a57"; 518 compatible = "arm,cortex-a57";
519 reg = <0x0 0x10101>; 519 reg = <0x0 0x10101>;
520 enable-method = "spin-table"; 520 enable-method = "spin-table";
521 cpu-release-addr = <0 0x20000000>; 521 cpu-release-addr = <0 0x20000000>;
522 }; 522 };
523 523
524 cpu@100000000 { 524 cpu@100000000 {
525 device_type = "cpu"; 525 device_type = "cpu";
526 compatible = "arm,cortex-a57"; 526 compatible = "arm,cortex-a57";
527 reg = <0x1 0x0>; 527 reg = <0x1 0x0>;
528 enable-method = "spin-table"; 528 enable-method = "spin-table";
529 cpu-release-addr = <0 0x20000000>; 529 cpu-release-addr = <0 0x20000000>;
530 }; 530 };
531 531
532 cpu@100000001 { 532 cpu@100000001 {
533 device_type = "cpu"; 533 device_type = "cpu";
534 compatible = "arm,cortex-a57"; 534 compatible = "arm,cortex-a57";
535 reg = <0x1 0x1>; 535 reg = <0x1 0x1>;
536 enable-method = "spin-table"; 536 enable-method = "spin-table";
537 cpu-release-addr = <0 0x20000000>; 537 cpu-release-addr = <0 0x20000000>;
538 }; 538 };
539 539
540 cpu@100000100 { 540 cpu@100000100 {
541 device_type = "cpu"; 541 device_type = "cpu";
542 compatible = "arm,cortex-a57"; 542 compatible = "arm,cortex-a57";
543 reg = <0x1 0x100>; 543 reg = <0x1 0x100>;
544 enable-method = "spin-table"; 544 enable-method = "spin-table";
545 cpu-release-addr = <0 0x20000000>; 545 cpu-release-addr = <0 0x20000000>;
546 }; 546 };
547 547
548 cpu@100000101 { 548 cpu@100000101 {
549 device_type = "cpu"; 549 device_type = "cpu";
550 compatible = "arm,cortex-a57"; 550 compatible = "arm,cortex-a57";
551 reg = <0x1 0x101>; 551 reg = <0x1 0x101>;
552 enable-method = "spin-table"; 552 enable-method = "spin-table";
553 cpu-release-addr = <0 0x20000000>; 553 cpu-release-addr = <0 0x20000000>;
554 }; 554 };
555 555
556 cpu@100010000 { 556 cpu@100010000 {
557 device_type = "cpu"; 557 device_type = "cpu";
558 compatible = "arm,cortex-a57"; 558 compatible = "arm,cortex-a57";
559 reg = <0x1 0x10000>; 559 reg = <0x1 0x10000>;
560 enable-method = "spin-table"; 560 enable-method = "spin-table";
561 cpu-release-addr = <0 0x20000000>; 561 cpu-release-addr = <0 0x20000000>;
562 }; 562 };
563 563
564 cpu@100010001 { 564 cpu@100010001 {
565 device_type = "cpu"; 565 device_type = "cpu";
566 compatible = "arm,cortex-a57"; 566 compatible = "arm,cortex-a57";
567 reg = <0x1 0x10001>; 567 reg = <0x1 0x10001>;
568 enable-method = "spin-table"; 568 enable-method = "spin-table";
569 cpu-release-addr = <0 0x20000000>; 569 cpu-release-addr = <0 0x20000000>;
570 }; 570 };
571 571
572 cpu@100010100 { 572 cpu@100010100 {
573 device_type = "cpu"; 573 device_type = "cpu";
574 compatible = "arm,cortex-a57"; 574 compatible = "arm,cortex-a57";
575 reg = <0x1 0x10100>; 575 reg = <0x1 0x10100>;
576 enable-method = "spin-table"; 576 enable-method = "spin-table";
577 cpu-release-addr = <0 0x20000000>; 577 cpu-release-addr = <0 0x20000000>;
578 }; 578 };
579 579
580 cpu@100010101 { 580 cpu@100010101 {
581 device_type = "cpu"; 581 device_type = "cpu";
582 compatible = "arm,cortex-a57"; 582 compatible = "arm,cortex-a57";
583 reg = <0x1 0x10101>; 583 reg = <0x1 0x10101>;
584 enable-method = "spin-table"; 584 enable-method = "spin-table";
585 cpu-release-addr = <0 0x20000000>; 585 cpu-release-addr = <0 0x20000000>;
586 }; 586 };
587 }; 587 };
588 ... 588 ...
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