1 Marvell Armada AP80x System Controller
2 ======================================
3
4 The AP806/AP807 is one of the two core HW bloc
5 7K/8K/931x SoCs. It contains system controller
6 registers giving access to numerous features:
7 many other SoC configuration items. This DT bi
8 these system controllers.
9
10 For the top level node:
11 - compatible: must be: "syscon", "simple-mfd"
12 - reg: register area of the AP80x system cont
13
14 SYSTEM CONTROLLER 0
15 ===================
16
17 Clocks:
18 -------
19
20
21 The Device Tree node representing the AP806/AP
22 provides a number of clocks:
23
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
28
29 Required properties:
30
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
33 * "marvell,ap807-clock"
34 - #clock-cells: must be set to 1
35
36 Pinctrl:
37 --------
38
39 For common binding part and usage, refer to
40 Documentation/devicetree/bindings/pinctrl/marv
41
42 Required properties:
43 - compatible must be "marvell,ap806-pinctrl",
44
45 Available mpp pins/groups and functions:
46 Note: brackets (x) are not part of the mpp nam
47 only for more detailed description in this doc
48
49 name pins functions
50 ==============================================
51 mpp0 0 gpio, sdio(clk), spi0(clk)
52 mpp1 1 gpio, sdio(cmd), spi0(miso)
53 mpp2 2 gpio, sdio(d0), spi0(mosi)
54 mpp3 3 gpio, sdio(d1), spi0(cs0n)
55 mpp4 4 gpio, sdio(d2), i2c0(sda)
56 mpp5 5 gpio, sdio(d3), i2c0(sdk)
57 mpp6 6 gpio, sdio(ds)
58 mpp7 7 gpio, sdio(d4), uart1(rxd)
59 mpp8 8 gpio, sdio(d5), uart1(txd)
60 mpp9 9 gpio, sdio(d6), spi0(cs1n)
61 mpp10 10 gpio, sdio(d7)
62 mpp11 11 gpio, uart0(txd)
63 mpp12 12 gpio, sdio(pw_off), sdio(hw_rs
64 mpp13 13 gpio
65 mpp14 14 gpio
66 mpp15 15 gpio
67 mpp16 16 gpio
68 mpp17 17 gpio
69 mpp18 18 gpio
70 mpp19 19 gpio, uart0(rxd), sdio(pw_off)
71
72 GPIO:
73 -----
74 For common binding part and usage, refer to
75 Documentation/devicetree/bindings/gpio/gpio-mv
76
77 Required properties:
78
79 - compatible: "marvell,armada-8k-gpio"
80
81 - offset: offset address inside the syscon blo
82
83 Optional properties:
84
85 - marvell,pwm-offset: offset address of PWM du
86 the syscon block
87
88 Example:
89 ap_syscon: system-controller@6f4000 {
90 compatible = "syscon", "simple-mfd";
91 reg = <0x6f4000 0x1000>;
92
93 ap_clk: clock {
94 compatible = "marvell,ap806-cl
95 #clock-cells = <1>;
96 };
97
98 ap_pinctrl: pinctrl {
99 compatible = "marvell,ap806-pi
100 };
101
102 ap_gpio: gpio {
103 compatible = "marvell,armada-8
104 offset = <0x1040>;
105 ngpios = <19>;
106 gpio-controller;
107 #gpio-cells = <2>;
108 gpio-ranges = <&ap_pinctrl 0 0
109 marvell,pwm-offset = <0x10c0>;
110 #pwm-cells = <2>;
111 clocks = <&ap_clk 3>;
112 };
113 };
114
115 SYSTEM CONTROLLER 1
116 ===================
117
118 Thermal:
119 --------
120
121 For common binding part and usage, refer to
122 Documentation/devicetree/bindings/thermal/ther
123
124 The thermal IP can probe the temperature all a
125 may feature several channels, each of them wir
126
127 It is possible to setup an overheat interrupt
128 critical point to any subnode of the thermal-z
129
130 Required properties:
131 - compatible: must be one of:
132 * marvell,armada-ap806-thermal
133 - reg: register range associated with the ther
134
135 Optional properties:
136 - interrupts: overheat interrupt handle. Shoul
137 SEI irqchip. See interrupt-controller/interr
138 - #thermal-sensor-cells: shall be <1> when the
139 to this IP and represents the channel ID. Th
140 channel. O refers to the thermal IP internal
141 IDs refer to each CPU.
142
143 Example:
144 ap_syscon1: system-controller@6f8000 {
145 compatible = "syscon", "simple-mfd";
146 reg = <0x6f8000 0x1000>;
147
148 ap_thermal: thermal-sensor@80 {
149 compatible = "marvell,armada-a
150 reg = <0x80 0x10>;
151 interrupt-parent = <&sei>;
152 interrupts = <18>;
153 #thermal-sensor-cells = <1>;
154 };
155 };
156
157 Cluster clocks:
158 ---------------
159
160 Device Tree Clock bindings for cluster clock o
161 AP806/AP807. Each cluster contain up to 2 CPUs
162 frequency.
163
164 Required properties:
165 - compatible: must be one of:
166 * "marvell,ap806-cpu-clock"
167 * "marvell,ap807-cpu-clock"
168 - #clock-cells : should be set to 1.
169
170 - clocks : shall be the input parent clock(s)
171 (one per cluster)
172
173 - reg: register range associated with the clus
174
175 ap_syscon1: system-controller@6f8000 {
176 compatible = "marvell,armada-ap806-sys
177 reg = <0x6f8000 0x1000>;
178
179 cpu_clk: clock-cpu@278 {
180 compatible = "marvell,ap806-cp
181 clocks = <&ap_clk 0>, <&ap_clk
182 #clock-cells = <1>;
183 reg = <0x278 0xa30>;
184 };
185 };
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