1 Marvell Armada AP80x System Controller 1 Marvell Armada AP80x System Controller
2 ====================================== 2 ======================================
3 3
4 The AP806/AP807 is one of the two core HW bloc 4 The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
5 7K/8K/931x SoCs. It contains system controller 5 7K/8K/931x SoCs. It contains system controllers, which provide several
6 registers giving access to numerous features: 6 registers giving access to numerous features: clocks, pin-muxing and
7 many other SoC configuration items. This DT bi 7 many other SoC configuration items. This DT binding allows to describe
8 these system controllers. 8 these system controllers.
9 9
10 For the top level node: 10 For the top level node:
11 - compatible: must be: "syscon", "simple-mfd" 11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system cont 12 - reg: register area of the AP80x system controller
13 13
14 SYSTEM CONTROLLER 0 14 SYSTEM CONTROLLER 0
15 =================== 15 ===================
16 16
17 Clocks: 17 Clocks:
18 ------- 18 -------
19 19
20 20
21 The Device Tree node representing the AP806/AP 21 The Device Tree node representing the AP806/AP807 system controller
22 provides a number of clocks: 22 provides a number of clocks:
23 23
24 - 0: reference clock of CPU cluster 0 24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1 25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz 26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL 27 - 3: MSS clock, derived from the fixed PLL
28 28
29 Required properties: 29 Required properties:
30 30
31 - compatible: must be one of: 31 - compatible: must be one of:
32 * "marvell,ap806-clock" 32 * "marvell,ap806-clock"
33 * "marvell,ap807-clock" 33 * "marvell,ap807-clock"
34 - #clock-cells: must be set to 1 34 - #clock-cells: must be set to 1
35 35
36 Pinctrl: 36 Pinctrl:
37 -------- 37 --------
38 38
39 For common binding part and usage, refer to 39 For common binding part and usage, refer to
40 Documentation/devicetree/bindings/pinctrl/marv 40 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
41 41
42 Required properties: 42 Required properties:
43 - compatible must be "marvell,ap806-pinctrl", 43 - compatible must be "marvell,ap806-pinctrl",
44 44
45 Available mpp pins/groups and functions: 45 Available mpp pins/groups and functions:
46 Note: brackets (x) are not part of the mpp nam 46 Note: brackets (x) are not part of the mpp name for marvell,function and given
47 only for more detailed description in this doc 47 only for more detailed description in this document.
48 48
49 name pins functions 49 name pins functions
50 ============================================== 50 ================================================================================
51 mpp0 0 gpio, sdio(clk), spi0(clk) 51 mpp0 0 gpio, sdio(clk), spi0(clk)
52 mpp1 1 gpio, sdio(cmd), spi0(miso) 52 mpp1 1 gpio, sdio(cmd), spi0(miso)
53 mpp2 2 gpio, sdio(d0), spi0(mosi) 53 mpp2 2 gpio, sdio(d0), spi0(mosi)
54 mpp3 3 gpio, sdio(d1), spi0(cs0n) 54 mpp3 3 gpio, sdio(d1), spi0(cs0n)
55 mpp4 4 gpio, sdio(d2), i2c0(sda) 55 mpp4 4 gpio, sdio(d2), i2c0(sda)
56 mpp5 5 gpio, sdio(d3), i2c0(sdk) 56 mpp5 5 gpio, sdio(d3), i2c0(sdk)
57 mpp6 6 gpio, sdio(ds) 57 mpp6 6 gpio, sdio(ds)
58 mpp7 7 gpio, sdio(d4), uart1(rxd) 58 mpp7 7 gpio, sdio(d4), uart1(rxd)
59 mpp8 8 gpio, sdio(d5), uart1(txd) 59 mpp8 8 gpio, sdio(d5), uart1(txd)
60 mpp9 9 gpio, sdio(d6), spi0(cs1n) 60 mpp9 9 gpio, sdio(d6), spi0(cs1n)
61 mpp10 10 gpio, sdio(d7) 61 mpp10 10 gpio, sdio(d7)
62 mpp11 11 gpio, uart0(txd) 62 mpp11 11 gpio, uart0(txd)
63 mpp12 12 gpio, sdio(pw_off), sdio(hw_rs 63 mpp12 12 gpio, sdio(pw_off), sdio(hw_rst)
64 mpp13 13 gpio 64 mpp13 13 gpio
65 mpp14 14 gpio 65 mpp14 14 gpio
66 mpp15 15 gpio 66 mpp15 15 gpio
67 mpp16 16 gpio 67 mpp16 16 gpio
68 mpp17 17 gpio 68 mpp17 17 gpio
69 mpp18 18 gpio 69 mpp18 18 gpio
70 mpp19 19 gpio, uart0(rxd), sdio(pw_off) 70 mpp19 19 gpio, uart0(rxd), sdio(pw_off)
71 71
72 GPIO: 72 GPIO:
73 ----- 73 -----
74 For common binding part and usage, refer to 74 For common binding part and usage, refer to
75 Documentation/devicetree/bindings/gpio/gpio-mv !! 75 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
76 76
77 Required properties: 77 Required properties:
78 78
79 - compatible: "marvell,armada-8k-gpio" 79 - compatible: "marvell,armada-8k-gpio"
80 80
81 - offset: offset address inside the syscon blo 81 - offset: offset address inside the syscon block
82 82
83 Optional properties: 83 Optional properties:
84 84
85 - marvell,pwm-offset: offset address of PWM du 85 - marvell,pwm-offset: offset address of PWM duration control registers inside
86 the syscon block 86 the syscon block
87 87
88 Example: 88 Example:
89 ap_syscon: system-controller@6f4000 { 89 ap_syscon: system-controller@6f4000 {
90 compatible = "syscon", "simple-mfd"; 90 compatible = "syscon", "simple-mfd";
91 reg = <0x6f4000 0x1000>; 91 reg = <0x6f4000 0x1000>;
92 92
93 ap_clk: clock { 93 ap_clk: clock {
94 compatible = "marvell,ap806-cl 94 compatible = "marvell,ap806-clock";
95 #clock-cells = <1>; 95 #clock-cells = <1>;
96 }; 96 };
97 97
98 ap_pinctrl: pinctrl { 98 ap_pinctrl: pinctrl {
99 compatible = "marvell,ap806-pi 99 compatible = "marvell,ap806-pinctrl";
100 }; 100 };
101 101
102 ap_gpio: gpio { 102 ap_gpio: gpio {
103 compatible = "marvell,armada-8 103 compatible = "marvell,armada-8k-gpio";
104 offset = <0x1040>; 104 offset = <0x1040>;
105 ngpios = <19>; 105 ngpios = <19>;
106 gpio-controller; 106 gpio-controller;
107 #gpio-cells = <2>; 107 #gpio-cells = <2>;
108 gpio-ranges = <&ap_pinctrl 0 0 108 gpio-ranges = <&ap_pinctrl 0 0 19>;
109 marvell,pwm-offset = <0x10c0>; 109 marvell,pwm-offset = <0x10c0>;
110 #pwm-cells = <2>; 110 #pwm-cells = <2>;
111 clocks = <&ap_clk 3>; 111 clocks = <&ap_clk 3>;
112 }; 112 };
113 }; 113 };
114 114
115 SYSTEM CONTROLLER 1 115 SYSTEM CONTROLLER 1
116 =================== 116 ===================
117 117
118 Thermal: 118 Thermal:
119 -------- 119 --------
120 120
121 For common binding part and usage, refer to 121 For common binding part and usage, refer to
122 Documentation/devicetree/bindings/thermal/ther 122 Documentation/devicetree/bindings/thermal/thermal*.yaml
123 123
124 The thermal IP can probe the temperature all a 124 The thermal IP can probe the temperature all around the processor. It
125 may feature several channels, each of them wir 125 may feature several channels, each of them wired to one sensor.
126 126
127 It is possible to setup an overheat interrupt 127 It is possible to setup an overheat interrupt by giving at least one
128 critical point to any subnode of the thermal-z 128 critical point to any subnode of the thermal-zone node.
129 129
130 Required properties: 130 Required properties:
131 - compatible: must be one of: 131 - compatible: must be one of:
132 * marvell,armada-ap806-thermal 132 * marvell,armada-ap806-thermal
133 - reg: register range associated with the ther 133 - reg: register range associated with the thermal functions.
134 134
135 Optional properties: 135 Optional properties:
136 - interrupts: overheat interrupt handle. Shoul 136 - interrupts: overheat interrupt handle. Should point to line 18 of the
137 SEI irqchip. See interrupt-controller/interr 137 SEI irqchip. See interrupt-controller/interrupts.txt
138 - #thermal-sensor-cells: shall be <1> when the 138 - #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
139 to this IP and represents the channel ID. Th 139 to this IP and represents the channel ID. There is one sensor per
140 channel. O refers to the thermal IP internal 140 channel. O refers to the thermal IP internal channel, while positive
141 IDs refer to each CPU. 141 IDs refer to each CPU.
142 142
143 Example: 143 Example:
144 ap_syscon1: system-controller@6f8000 { 144 ap_syscon1: system-controller@6f8000 {
145 compatible = "syscon", "simple-mfd"; 145 compatible = "syscon", "simple-mfd";
146 reg = <0x6f8000 0x1000>; 146 reg = <0x6f8000 0x1000>;
147 147
148 ap_thermal: thermal-sensor@80 { 148 ap_thermal: thermal-sensor@80 {
149 compatible = "marvell,armada-a 149 compatible = "marvell,armada-ap806-thermal";
150 reg = <0x80 0x10>; 150 reg = <0x80 0x10>;
151 interrupt-parent = <&sei>; 151 interrupt-parent = <&sei>;
152 interrupts = <18>; 152 interrupts = <18>;
153 #thermal-sensor-cells = <1>; 153 #thermal-sensor-cells = <1>;
154 }; 154 };
155 }; 155 };
156 156
157 Cluster clocks: 157 Cluster clocks:
158 --------------- 158 ---------------
159 159
160 Device Tree Clock bindings for cluster clock o 160 Device Tree Clock bindings for cluster clock of Marvell
161 AP806/AP807. Each cluster contain up to 2 CPUs 161 AP806/AP807. Each cluster contain up to 2 CPUs running at the same
162 frequency. 162 frequency.
163 163
164 Required properties: 164 Required properties:
165 - compatible: must be one of: 165 - compatible: must be one of:
166 * "marvell,ap806-cpu-clock" 166 * "marvell,ap806-cpu-clock"
167 * "marvell,ap807-cpu-clock" 167 * "marvell,ap807-cpu-clock"
168 - #clock-cells : should be set to 1. 168 - #clock-cells : should be set to 1.
169 169
170 - clocks : shall be the input parent clock(s) 170 - clocks : shall be the input parent clock(s) phandle for the clock
171 (one per cluster) 171 (one per cluster)
172 172
173 - reg: register range associated with the clus 173 - reg: register range associated with the cluster clocks
174 174
175 ap_syscon1: system-controller@6f8000 { 175 ap_syscon1: system-controller@6f8000 {
176 compatible = "marvell,armada-ap806-sys 176 compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
177 reg = <0x6f8000 0x1000>; 177 reg = <0x6f8000 0x1000>;
178 178
179 cpu_clk: clock-cpu@278 { 179 cpu_clk: clock-cpu@278 {
180 compatible = "marvell,ap806-cp 180 compatible = "marvell,ap806-cpu-clock";
181 clocks = <&ap_clk 0>, <&ap_clk 181 clocks = <&ap_clk 0>, <&ap_clk 1>;
182 #clock-cells = <1>; 182 #clock-cells = <1>;
183 reg = <0x278 0xa30>; 183 reg = <0x278 0xa30>;
184 }; 184 };
185 }; 185 };
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