1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/arm/pmu.yam 4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ARM Performance Monitor Units 7 title: ARM Performance Monitor Units
8 8
9 maintainers: 9 maintainers:
10 - Mark Rutland <mark.rutland@arm.com> 10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com> 11 - Will Deacon <will.deacon@arm.com>
12 12
13 description: |+ 13 description: |+
14 ARM cores often have a PMU for counting cpu 14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part o 15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
16 representation in the device tree should be 16 representation in the device tree should be done as under:-
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 items: 20 items:
21 - enum: 21 - enum:
22 - apm,potenza-pmu 22 - apm,potenza-pmu
23 - apple,avalanche-pmu 23 - apple,avalanche-pmu
24 - apple,blizzard-pmu 24 - apple,blizzard-pmu
25 - apple,firestorm-pmu 25 - apple,firestorm-pmu
26 - apple,icestorm-pmu 26 - apple,icestorm-pmu
27 - arm,armv8-pmuv3 # Only for s/w mod 27 - arm,armv8-pmuv3 # Only for s/w models
28 - arm,arm1136-pmu 28 - arm,arm1136-pmu
29 - arm,arm1176-pmu 29 - arm,arm1176-pmu
30 - arm,arm11mpcore-pmu 30 - arm,arm11mpcore-pmu
31 - arm,cortex-a5-pmu 31 - arm,cortex-a5-pmu
32 - arm,cortex-a7-pmu 32 - arm,cortex-a7-pmu
33 - arm,cortex-a8-pmu 33 - arm,cortex-a8-pmu
34 - arm,cortex-a9-pmu 34 - arm,cortex-a9-pmu
35 - arm,cortex-a12-pmu 35 - arm,cortex-a12-pmu
36 - arm,cortex-a15-pmu 36 - arm,cortex-a15-pmu
37 - arm,cortex-a17-pmu 37 - arm,cortex-a17-pmu
38 - arm,cortex-a32-pmu 38 - arm,cortex-a32-pmu
39 - arm,cortex-a34-pmu 39 - arm,cortex-a34-pmu
40 - arm,cortex-a35-pmu 40 - arm,cortex-a35-pmu
41 - arm,cortex-a53-pmu 41 - arm,cortex-a53-pmu
42 - arm,cortex-a55-pmu 42 - arm,cortex-a55-pmu
43 - arm,cortex-a57-pmu 43 - arm,cortex-a57-pmu
44 - arm,cortex-a65-pmu 44 - arm,cortex-a65-pmu
45 - arm,cortex-a72-pmu 45 - arm,cortex-a72-pmu
46 - arm,cortex-a73-pmu 46 - arm,cortex-a73-pmu
47 - arm,cortex-a75-pmu 47 - arm,cortex-a75-pmu
48 - arm,cortex-a76-pmu 48 - arm,cortex-a76-pmu
49 - arm,cortex-a77-pmu 49 - arm,cortex-a77-pmu
50 - arm,cortex-a78-pmu 50 - arm,cortex-a78-pmu
51 - arm,cortex-a510-pmu 51 - arm,cortex-a510-pmu
52 - arm,cortex-a520-pmu 52 - arm,cortex-a520-pmu
53 - arm,cortex-a710-pmu 53 - arm,cortex-a710-pmu
54 - arm,cortex-a715-pmu 54 - arm,cortex-a715-pmu
55 - arm,cortex-a720-pmu 55 - arm,cortex-a720-pmu
56 - arm,cortex-a725-pmu 56 - arm,cortex-a725-pmu
57 - arm,cortex-x1-pmu 57 - arm,cortex-x1-pmu
58 - arm,cortex-x2-pmu 58 - arm,cortex-x2-pmu
59 - arm,cortex-x3-pmu 59 - arm,cortex-x3-pmu
60 - arm,cortex-x4-pmu 60 - arm,cortex-x4-pmu
61 - arm,cortex-x925-pmu 61 - arm,cortex-x925-pmu
62 - arm,neoverse-e1-pmu 62 - arm,neoverse-e1-pmu
63 - arm,neoverse-n1-pmu 63 - arm,neoverse-n1-pmu
64 - arm,neoverse-n2-pmu 64 - arm,neoverse-n2-pmu
65 - arm,neoverse-n3-pmu 65 - arm,neoverse-n3-pmu
66 - arm,neoverse-v1-pmu 66 - arm,neoverse-v1-pmu
67 - arm,neoverse-v2-pmu 67 - arm,neoverse-v2-pmu
68 - arm,neoverse-v3-pmu 68 - arm,neoverse-v3-pmu
69 - arm,neoverse-v3ae-pmu 69 - arm,neoverse-v3ae-pmu
70 - brcm,vulcan-pmu 70 - brcm,vulcan-pmu
71 - cavium,thunder-pmu 71 - cavium,thunder-pmu
72 - nvidia,denver-pmu 72 - nvidia,denver-pmu
73 - nvidia,carmel-pmu 73 - nvidia,carmel-pmu
74 - qcom,krait-pmu 74 - qcom,krait-pmu
75 - qcom,scorpion-pmu 75 - qcom,scorpion-pmu
76 - qcom,scorpion-mp-pmu 76 - qcom,scorpion-mp-pmu
77 77
78 interrupts: 78 interrupts:
79 # Don't know how many CPUs, so no constrai 79 # Don't know how many CPUs, so no constraints to specify
80 description: 1 per-cpu interrupt (PPI) or 80 description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
81 81
82 interrupt-affinity: 82 interrupt-affinity:
83 $ref: /schemas/types.yaml#/definitions/pha 83 $ref: /schemas/types.yaml#/definitions/phandle-array
84 items: 84 items:
85 maxItems: 1 85 maxItems: 1
86 description: 86 description:
87 When using SPIs, specifies a list of pha 87 When using SPIs, specifies a list of phandles to CPU
88 nodes corresponding directly to the affi 88 nodes corresponding directly to the affinity of
89 the SPIs listed in the interrupts proper 89 the SPIs listed in the interrupts property.
90 90
91 When using a PPI, specifies a list of ph 91 When using a PPI, specifies a list of phandles to CPU
92 nodes corresponding to the set of CPUs w 92 nodes corresponding to the set of CPUs which have
93 a PMU of this type signalling the PPI li 93 a PMU of this type signalling the PPI listed in the
94 interrupts property, unless this is alre 94 interrupts property, unless this is already specified
95 by the PPI interrupt specifier itself (i 95 by the PPI interrupt specifier itself (in which case
96 the interrupt-affinity property shouldn' 96 the interrupt-affinity property shouldn't be present).
97 97
98 This property should be present when the 98 This property should be present when there is more than
99 a single SPI. 99 a single SPI.
100 100
101 qcom,no-pc-write: 101 qcom,no-pc-write:
102 type: boolean 102 type: boolean
103 description: 103 description:
104 Indicates that this PMU doesn't support 104 Indicates that this PMU doesn't support the 0xc and 0xd events.
105 105
106 secure-reg-access: 106 secure-reg-access:
107 type: boolean 107 type: boolean
108 description: 108 description:
109 Indicates that the ARMv7 Secure Debug En 109 Indicates that the ARMv7 Secure Debug Enable Register
110 (SDER) is accessible. This will cause th 110 (SDER) is accessible. This will cause the driver to do
111 any setup required that is only possible 111 any setup required that is only possible in ARMv7 secure
112 state. If not present the ARMv7 SDER wil 112 state. If not present the ARMv7 SDER will not be touched,
113 which means the PMU may fail to operate 113 which means the PMU may fail to operate unless external
114 code (bootloader or security monitor) ha 114 code (bootloader or security monitor) has performed the
115 appropriate initialisation. Note that th 115 appropriate initialisation. Note that this property is
116 not valid for non-ARMv7 CPUs or ARMv7 CP 116 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
117 in Non-secure state. 117 in Non-secure state.
118 118
119 required: 119 required:
120 - compatible 120 - compatible
121 121
122 additionalProperties: false 122 additionalProperties: false
123 123
124 ... 124 ...
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