1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/arm/sp810.y 4 $id: http://devicetree.org/schemas/arm/sp810.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ARM Versatile Express SP810 System Cont 7 title: ARM Versatile Express SP810 System Controller
8 8
9 maintainers: 9 maintainers:
10 - Andre Przywara <andre.przywara@arm.com> 10 - Andre Przywara <andre.przywara@arm.com>
11 11
12 description: 12 description:
13 The Arm SP810 system controller provides clo 13 The Arm SP810 system controller provides clocks, timers and a watchdog.
14 14
15 # We need a select here so we don't match all 15 # We need a select here so we don't match all nodes with 'arm,primecell'
16 select: 16 select:
17 properties: 17 properties:
18 compatible: 18 compatible:
19 contains: 19 contains:
20 const: arm,sp810 20 const: arm,sp810
21 required: 21 required:
22 - compatible 22 - compatible
23 23
24 properties: 24 properties:
25 compatible: 25 compatible:
26 items: 26 items:
27 - const: arm,sp810 27 - const: arm,sp810
28 - const: arm,primecell 28 - const: arm,primecell
29 29
30 reg: 30 reg:
31 maxItems: 1 31 maxItems: 1
32 32
33 clock-names: 33 clock-names:
34 items: 34 items:
35 - const: refclk 35 - const: refclk
36 - const: timclk 36 - const: timclk
37 - const: apb_pclk 37 - const: apb_pclk
38 38
39 clocks: 39 clocks:
40 items: 40 items:
41 - description: reference clock 41 - description: reference clock
42 - description: timer clock 42 - description: timer clock
43 - description: APB register access clock 43 - description: APB register access clock
44 44
45 "#clock-cells": 45 "#clock-cells":
46 const: 1 46 const: 1
47 47
48 clock-output-names: 48 clock-output-names:
49 maxItems: 4 49 maxItems: 4
50 50
51 assigned-clocks: 51 assigned-clocks:
52 maxItems: 4 52 maxItems: 4
53 53
54 assigned-clock-parents: 54 assigned-clock-parents:
55 maxItems: 4 55 maxItems: 4
56 56
57 additionalProperties: false 57 additionalProperties: false
58 58
59 required: 59 required:
60 - compatible 60 - compatible
61 - reg 61 - reg
62 - clocks 62 - clocks
63 - clock-names 63 - clock-names
64 - "#clock-cells" 64 - "#clock-cells"
65 65
66 examples: 66 examples:
67 - | 67 - |
68 sysctl@20000 { 68 sysctl@20000 {
69 compatible = "arm,sp810", "arm,primece 69 compatible = "arm,sp810", "arm,primecell";
70 reg = <0x020000 0x1000>; 70 reg = <0x020000 0x1000>;
71 clocks = <&v2m_refclk32khz>, <&v2m_ref 71 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
72 clock-names = "refclk", "timclk", "apb 72 clock-names = "refclk", "timclk", "apb_pclk";
73 #clock-cells = <1>; 73 #clock-cells = <1>;
74 clock-output-names = "timerclken0", "t 74 clock-output-names = "timerclken0", "timerclken1",
75 "timerclken2", "t 75 "timerclken2", "timerclken3";
76 assigned-clocks = <&v2m_sysctl 0>, <&v 76 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>,
77 <&v2m_sysctl 3>, <&v 77 <&v2m_sysctl 3>, <&v2m_sysctl 3>;
78 assigned-clock-parents = <&v2m_refclk1 78 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>,
79 <&v2m_refclk1 79 <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
80 }; 80 };
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