1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/cache/baika 5 $id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 7
8 title: Baikal-T1 L2-cache Control Block 8 title: Baikal-T1 L2-cache Control Block
9 9
10 maintainers: 10 maintainers:
11 - Serge Semin <fancer.lancer@gmail.com> 11 - Serge Semin <fancer.lancer@gmail.com>
12 12
13 description: | 13 description: |
14 By means of the System Controller Baikal-T1 14 By means of the System Controller Baikal-T1 SoC exposes a few settings to
15 tune the MIPS P5600 CM2 L2 cache performance 15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
16 to change the Tag, Data and Way-select RAM a 16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
17 L2-cache controller block is responsible for 17 L2-cache controller block is responsible for the tuning. Its DT node is
18 supposed to be a child of the system control 18 supposed to be a child of the system controller.
19 19
20 properties: 20 properties:
21 compatible: 21 compatible:
22 const: baikal,bt1-l2-ctl 22 const: baikal,bt1-l2-ctl
23 23
24 reg: 24 reg:
25 maxItems: 1 25 maxItems: 1
26 26
27 baikal,l2-ws-latency: 27 baikal,l2-ws-latency:
28 $ref: /schemas/types.yaml#/definitions/uin 28 $ref: /schemas/types.yaml#/definitions/uint32
29 description: Cycles of latency for Way-sel 29 description: Cycles of latency for Way-select RAM accesses
30 default: 0 30 default: 0
31 minimum: 0 31 minimum: 0
32 maximum: 3 32 maximum: 3
33 33
34 baikal,l2-tag-latency: 34 baikal,l2-tag-latency:
35 $ref: /schemas/types.yaml#/definitions/uin 35 $ref: /schemas/types.yaml#/definitions/uint32
36 description: Cycles of latency for Tag RAM 36 description: Cycles of latency for Tag RAM accesses
37 default: 0 37 default: 0
38 minimum: 0 38 minimum: 0
39 maximum: 3 39 maximum: 3
40 40
41 baikal,l2-data-latency: 41 baikal,l2-data-latency:
42 $ref: /schemas/types.yaml#/definitions/uin 42 $ref: /schemas/types.yaml#/definitions/uint32
43 description: Cycles of latency for Data RA 43 description: Cycles of latency for Data RAM accesses
44 default: 1 44 default: 1
45 minimum: 0 45 minimum: 0
46 maximum: 3 46 maximum: 3
47 47
48 additionalProperties: false 48 additionalProperties: false
49 49
50 required: 50 required:
51 - compatible 51 - compatible
52 52
53 examples: 53 examples:
54 - | 54 - |
55 l2@1f04d028 { 55 l2@1f04d028 {
56 compatible = "baikal,bt1-l2-ctl"; 56 compatible = "baikal,bt1-l2-ctl";
57 reg = <0x1f04d028 0x004>; 57 reg = <0x1f04d028 0x004>;
58 58
59 baikal,l2-ws-latency = <1>; 59 baikal,l2-ws-latency = <1>;
60 baikal,l2-tag-latency = <1>; 60 baikal,l2-tag-latency = <1>;
61 baikal,l2-data-latency = <2>; 61 baikal,l2-data-latency = <2>;
62 }; 62 };
63 ... 63 ...
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