1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/allwi 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Allwinner A10 CPU PLL !! 7 title: Allwinner A10 CPU PLL Device Tree Bindings
8 8
9 maintainers: 9 maintainers:
10 - Chen-Yu Tsai <wens@csie.org> 10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org> 11 - Maxime Ripard <mripard@kernel.org>
12 12
13 deprecated: true 13 deprecated: true
14 14
15 properties: 15 properties:
16 "#clock-cells": 16 "#clock-cells":
17 const: 0 17 const: 0
18 18
19 compatible: 19 compatible:
20 enum: 20 enum:
21 - allwinner,sun4i-a10-pll1-clk 21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk 22 - allwinner,sun6i-a31-pll1-clk
23 - allwinner,sun8i-a23-pll1-clk 23 - allwinner,sun8i-a23-pll1-clk
24 24
25 reg: 25 reg:
26 maxItems: 1 26 maxItems: 1
27 27
28 clocks: 28 clocks:
29 maxItems: 1 29 maxItems: 1
30 30
31 clock-output-names: 31 clock-output-names:
32 maxItems: 1 32 maxItems: 1
33 33
34 required: 34 required:
35 - "#clock-cells" 35 - "#clock-cells"
36 - compatible 36 - compatible
37 - reg 37 - reg
38 - clocks 38 - clocks
39 - clock-output-names 39 - clock-output-names
40 40
41 additionalProperties: false 41 additionalProperties: false
42 42
43 examples: 43 examples:
44 - | 44 - |
45 clk@1c20000 { 45 clk@1c20000 {
46 #clock-cells = <0>; 46 #clock-cells = <0>;
47 compatible = "allwinner,sun4i-a10-pll1 !! 47 compatible = "allwinner,sun4i-a10-pll1";
48 reg = <0x01c20000 0x4>; 48 reg = <0x01c20000 0x4>;
49 clocks = <&osc24M>; 49 clocks = <&osc24M>;
50 clock-output-names = "osc24M"; 50 clock-output-names = "osc24M";
51 }; 51 };
52 52
53 - | 53 - |
54 clk@1c20000 { 54 clk@1c20000 {
55 #clock-cells = <0>; 55 #clock-cells = <0>;
56 compatible = "allwinner,sun6i-a31-pll1 56 compatible = "allwinner,sun6i-a31-pll1-clk";
57 reg = <0x01c20000 0x4>; 57 reg = <0x01c20000 0x4>;
58 clocks = <&osc24M>; 58 clocks = <&osc24M>;
59 clock-output-names = "pll1"; 59 clock-output-names = "pll1";
60 }; 60 };
61 61
62 - | 62 - |
63 clk@1c20000 { 63 clk@1c20000 {
64 #clock-cells = <0>; 64 #clock-cells = <0>;
65 compatible = "allwinner,sun8i-a23-pll1 65 compatible = "allwinner,sun8i-a23-pll1-clk";
66 reg = <0x01c20000 0x4>; 66 reg = <0x01c20000 0x4>;
67 clocks = <&osc24M>; 67 clocks = <&osc24M>;
68 clock-output-names = "pll1"; 68 clock-output-names = "pll1";
69 }; 69 };
70 70
71 ... 71 ...
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