1 # SPDX-License-Identifier: GPL-2.0-only OR BSD
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/amlog
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Amlogic AXG Audio Clock Controller
8
9 maintainers:
10 - Neil Armstrong <neil.armstrong@linaro.org>
11 - Jerome Brunet <jbrunet@baylibre.com>
12
13 description:
14 The Amlogic AXG audio clock controller gener
15 other elements of the audio subsystem, such
16 devices.
17
18 properties:
19 compatible:
20 enum:
21 - amlogic,axg-audio-clkc
22 - amlogic,g12a-audio-clkc
23 - amlogic,sm1-audio-clkc
24
25 '#clock-cells':
26 const: 1
27
28 '#reset-cells':
29 const: 1
30
31 reg:
32 maxItems: 1
33
34 clocks:
35 minItems: 1
36 items:
37 - description: main peripheral bus clock
38 - description: input plls to generate cl
39 - description: input plls to generate cl
40 - description: input plls to generate cl
41 - description: input plls to generate cl
42 - description: input plls to generate cl
43 - description: input plls to generate cl
44 - description: input plls to generate cl
45 - description: input plls to generate cl
46 - description: slave bit clock N0 provid
47 - description: slave bit clock N1 provid
48 - description: slave bit clock N2 provid
49 - description: slave bit clock N3 provid
50 - description: slave bit clock N4 provid
51 - description: slave bit clock N5 provid
52 - description: slave bit clock N6 provid
53 - description: slave bit clock N7 provid
54 - description: slave bit clock N8 provid
55 - description: slave bit clock N9 provid
56 - description: slave sample clock N0 pro
57 - description: slave sample clock N1 pro
58 - description: slave sample clock N2 pro
59 - description: slave sample clock N3 pro
60 - description: slave sample clock N4 pro
61 - description: slave sample clock N5 pro
62 - description: slave sample clock N6 pro
63 - description: slave sample clock N7 pro
64 - description: slave sample clock N8 pro
65 - description: slave sample clock N9 pro
66
67 clock-names:
68 minItems: 1
69 items:
70 - const: pclk
71 - const: mst_in0
72 - const: mst_in1
73 - const: mst_in2
74 - const: mst_in3
75 - const: mst_in4
76 - const: mst_in5
77 - const: mst_in6
78 - const: mst_in7
79 - const: slv_sclk0
80 - const: slv_sclk1
81 - const: slv_sclk2
82 - const: slv_sclk3
83 - const: slv_sclk4
84 - const: slv_sclk5
85 - const: slv_sclk6
86 - const: slv_sclk7
87 - const: slv_sclk8
88 - const: slv_sclk9
89 - const: slv_lrclk0
90 - const: slv_lrclk1
91 - const: slv_lrclk2
92 - const: slv_lrclk3
93 - const: slv_lrclk4
94 - const: slv_lrclk5
95 - const: slv_lrclk6
96 - const: slv_lrclk7
97 - const: slv_lrclk8
98 - const: slv_lrclk9
99
100 resets:
101 description: internal reset line
102
103 required:
104 - compatible
105 - '#clock-cells'
106 - reg
107 - clocks
108 - clock-names
109 - resets
110
111 allOf:
112 - if:
113 properties:
114 compatible:
115 contains:
116 enum:
117 - amlogic,g12a-audio-clkc
118 - amlogic,sm1-audio-clkc
119 then:
120 required:
121 - '#reset-cells'
122 else:
123 properties:
124 '#reset-cells': false
125
126 additionalProperties: false
127
128 examples:
129 - |
130 #include <dt-bindings/clock/axg-clkc.h>
131 #include <dt-bindings/reset/amlogic,meson-
132 apb {
133 #address-cells = <2>;
134 #size-cells = <2>;
135
136 clkc_audio: clock-controller@0 {
137 compatible = "amlogic,axg-audio-cl
138 reg = <0x0 0x0 0x0 0xb4>;
139 #clock-cells = <1>;
140
141 clocks = <&clkc CLKID_AUDIO>,
142 <&clkc CLKID_MPLL0>,
143 <&clkc CLKID_MPLL1>,
144 <&clkc CLKID_MPLL2>,
145 <&clkc CLKID_MPLL3>,
146 <&clkc CLKID_HIFI_PLL>,
147 <&clkc CLKID_FCLK_DIV3>,
148 <&clkc CLKID_FCLK_DIV4>,
149 <&clkc CLKID_GP0_PLL>,
150 <&slv_sclk0>,
151 <&slv_sclk1>,
152 <&slv_sclk2>,
153 <&slv_sclk3>,
154 <&slv_sclk4>,
155 <&slv_sclk5>,
156 <&slv_sclk6>,
157 <&slv_sclk7>,
158 <&slv_sclk8>,
159 <&slv_sclk9>,
160 <&slv_lrclk0>,
161 <&slv_lrclk1>,
162 <&slv_lrclk2>,
163 <&slv_lrclk3>,
164 <&slv_lrclk4>,
165 <&slv_lrclk5>,
166 <&slv_lrclk6>,
167 <&slv_lrclk7>,
168 <&slv_lrclk8>,
169 <&slv_lrclk9>;
170 clock-names = "pclk",
171 "mst_in0",
172 "mst_in1",
173 "mst_in2",
174 "mst_in3",
175 "mst_in4",
176 "mst_in5",
177 "mst_in6",
178 "mst_in7",
179 "slv_sclk0",
180 "slv_sclk1",
181 "slv_sclk2",
182 "slv_sclk3",
183 "slv_sclk4",
184 "slv_sclk5",
185 "slv_sclk6",
186 "slv_sclk7",
187 "slv_sclk8",
188 "slv_sclk9",
189 "slv_lrclk0",
190 "slv_lrclk1",
191 "slv_lrclk2",
192 "slv_lrclk3",
193 "slv_lrclk4",
194 "slv_lrclk5",
195 "slv_lrclk6",
196 "slv_lrclk7",
197 "slv_lrclk8",
198 "slv_lrclk9";
199 resets = <&reset RESET_AUDIO>;
200 };
201 };
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