1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Amlogic, Inc. All ri 2 # Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/clock/amlog 5 $id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 7
8 title: Amlogic C3 series PLL Clock Controller 8 title: Amlogic C3 series PLL Clock Controller
9 9
10 maintainers: 10 maintainers:
11 - Neil Armstrong <neil.armstrong@linaro.org> 11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Jerome Brunet <jbrunet@baylibre.com> 12 - Jerome Brunet <jbrunet@baylibre.com>
13 - Chuan Liu <chuan.liu@amlogic.com> 13 - Chuan Liu <chuan.liu@amlogic.com>
14 - Xianwei Zhao <xianwei.zhao@amlogic.com> 14 - Xianwei Zhao <xianwei.zhao@amlogic.com>
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 const: amlogic,c3-pll-clkc 18 const: amlogic,c3-pll-clkc
19 19
20 reg: 20 reg:
21 maxItems: 1 21 maxItems: 1
22 22
23 clocks: 23 clocks:
24 items: 24 items:
25 - description: input top pll 25 - description: input top pll
26 - description: input mclk pll 26 - description: input mclk pll
27 - description: input fix pll <<
28 27
29 clock-names: 28 clock-names:
30 items: 29 items:
31 - const: top 30 - const: top
32 - const: mclk 31 - const: mclk
33 - const: fix <<
34 32
35 "#clock-cells": 33 "#clock-cells":
36 const: 1 34 const: 1
37 35
38 required: 36 required:
39 - compatible 37 - compatible
40 - reg 38 - reg
41 - clocks 39 - clocks
42 - clock-names 40 - clock-names
43 - "#clock-cells" 41 - "#clock-cells"
44 42
45 additionalProperties: false 43 additionalProperties: false
46 44
47 examples: 45 examples:
48 - | 46 - |
49 apb { 47 apb {
50 #address-cells = <2>; 48 #address-cells = <2>;
51 #size-cells = <2>; 49 #size-cells = <2>;
52 50
53 clock-controller@8000 { 51 clock-controller@8000 {
54 compatible = "amlogic,c3-pll-clkc" 52 compatible = "amlogic,c3-pll-clkc";
55 reg = <0x0 0x8000 0x0 0x1a4>; 53 reg = <0x0 0x8000 0x0 0x1a4>;
56 clocks = <&scmi_clk 2>, 54 clocks = <&scmi_clk 2>,
57 <&scmi_clk 5>, !! 55 <&scmi_clk 5>;
58 <&scmi_clk 12>; !! 56 clock-names = "top", "mclk";
59 clock-names = "top", "mclk", "fix" <<
60 #clock-cells = <1>; 57 #clock-cells = <1>;
61 }; 58 };
62 }; 59 };
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