1 * Clock bindings for Axis ARTPEC-6 chip 1 * Clock bindings for Axis ARTPEC-6 chip
2 2
3 The bindings are based on the clock provider b 3 The bindings are based on the clock provider binding in
4 Documentation/devicetree/bindings/clock/clock- 4 Documentation/devicetree/bindings/clock/clock-bindings.txt
5 5
6 External clocks: 6 External clocks:
7 ---------------- 7 ----------------
8 8
9 There are two external inputs to the main cloc 9 There are two external inputs to the main clock controller which should be
10 provided using the common clock bindings. 10 provided using the common clock bindings.
11 - "sys_refclk": External 50 Mhz oscillator (re 11 - "sys_refclk": External 50 Mhz oscillator (required)
12 - "i2s_refclk": Alternate audio reference cloc 12 - "i2s_refclk": Alternate audio reference clock (optional).
13 13
14 Main clock controller 14 Main clock controller
15 --------------------- 15 ---------------------
16 16
17 Required properties: 17 Required properties:
18 - #clock-cells: Should be <1> 18 - #clock-cells: Should be <1>
19 See dt-bindings/clock/axis,artpec6-clkctrl.h 19 See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
20 - compatible: Should be "axis,artpec6-clkctrl" 20 - compatible: Should be "axis,artpec6-clkctrl"
21 - reg: Must contain the base address and lengt 21 - reg: Must contain the base address and length of the system controller
22 - clocks: Must contain a phandle entry for ea 22 - clocks: Must contain a phandle entry for each clock in clock-names
23 - clock-names: Must include the external oscil 23 - clock-names: Must include the external oscillator ("sys_refclk"). Optional
24 ones are the audio reference clock ("i2s_ref 24 ones are the audio reference clock ("i2s_refclk") and the audio fractional
25 dividers ("frac_clk0" and "frac_clk1"). 25 dividers ("frac_clk0" and "frac_clk1").
26 26
27 Examples: 27 Examples:
28 28
29 ext_clk: ext_clk { 29 ext_clk: ext_clk {
30 #clock-cells = <0>; 30 #clock-cells = <0>;
31 compatible = "fixed-clock"; 31 compatible = "fixed-clock";
32 clock-frequency = <50000000>; 32 clock-frequency = <50000000>;
33 }; 33 };
34 34
35 clkctrl: clkctrl@f8000000 { 35 clkctrl: clkctrl@f8000000 {
36 #clock-cells = <1>; 36 #clock-cells = <1>;
37 compatible = "axis,artpec6-clkctrl"; 37 compatible = "axis,artpec6-clkctrl";
38 reg = <0xf8000000 0x48>; 38 reg = <0xf8000000 0x48>;
39 clocks = <&ext_clk>; 39 clocks = <&ext_clk>;
40 clock-names = "sys_refclk"; 40 clock-names = "sys_refclk";
41 }; 41 };
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