1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/cirru
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: CIRRUS LOGIC Fractional-N Clock Synthes
8
9 maintainers:
10 - Kuninori Morimoto <kuninori.morimoto.gx@ren
11
12 description: |
13 The CS2000-CP is an extremely versatile syst
14 utilizes a programmable phase lock loop.
15
16 Link: https://www.cirrus.com/products/cs2000
17
18 properties:
19 compatible:
20 enum:
21 - cirrus,cs2000-cp
22
23 clocks:
24 description:
25 Common clock binding for CLK_IN, XTI/REF
26 maxItems: 2
27
28 clock-names:
29 items:
30 - const: clk_in
31 - const: ref_clk
32
33 '#clock-cells':
34 const: 0
35
36 reg:
37 maxItems: 1
38
39 cirrus,aux-output-source:
40 description:
41 Specifies the function of the auxiliary
42 $ref: /schemas/types.yaml#/definitions/uin
43 enum:
44 - 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_
45 - 1 # CS2000CP_AUX_OUTPUT_CLK_IN: clk_
46 - 2 # CS2000CP_AUX_OUTPUT_CLK_OUT: clk_
47 - 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll
48 default: 0
49
50 cirrus,clock-skip:
51 description:
52 This mode allows the PLL to maintain loc
53 has missing pulses for up to 20 ms.
54 $ref: /schemas/types.yaml#/definitions/fla
55
56 cirrus,dynamic-mode:
57 description:
58 In dynamic mode, the CLK_IN input is use
59 digital PLL of the silicon.
60 If not given, the static mode shall be u
61 output signal directly from the REF_CLK
62 $ref: /schemas/types.yaml#/definitions/fla
63
64 required:
65 - compatible
66 - reg
67 - clocks
68 - clock-names
69 - '#clock-cells'
70
71 additionalProperties: false
72
73 examples:
74 - |
75 #include <dt-bindings/clock/cirrus,cs2000-
76
77 i2c@0 {
78 reg = <0x0 0x100>;
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 clock-controller@4f {
83 #clock-cells = <0>;
84 compatible = "cirrus,cs2000-cp";
85 reg = <0x4f>;
86 clocks = <&rcar_sound 0>, <&x12_clk>;
87 clock-names = "clk_in", "ref_clk";
88 cirrus,aux-output-source = <CS2000CP_A
89 };
90 };
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