1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/fixed 4 $id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Simple memory mapped IO fixed-rate cloc 7 title: Simple memory mapped IO fixed-rate clock sources
8 8
9 description: 9 description:
10 This binding describes a fixed-rate clock fo 10 This binding describes a fixed-rate clock for which the frequency can
11 be read from a single 32-bit memory mapped I 11 be read from a single 32-bit memory mapped I/O register.
12 12
13 It was designed for test systems, like FPGA, 13 It was designed for test systems, like FPGA, not for complete,
14 finished SoCs. 14 finished SoCs.
15 15
16 maintainers: 16 maintainers:
17 - Jan Kotas <jank@cadence.com> 17 - Jan Kotas <jank@cadence.com>
18 18
19 properties: 19 properties:
20 compatible: 20 compatible:
21 const: fixed-mmio-clock 21 const: fixed-mmio-clock
22 22
23 reg: 23 reg:
24 maxItems: 1 24 maxItems: 1
25 25
26 "#clock-cells": 26 "#clock-cells":
27 const: 0 27 const: 0
28 28
29 clock-output-names: 29 clock-output-names:
30 maxItems: 1 30 maxItems: 1
31 31
32 required: 32 required:
33 - compatible 33 - compatible
34 - reg 34 - reg
35 - "#clock-cells" 35 - "#clock-cells"
36 36
37 additionalProperties: false 37 additionalProperties: false
38 38
39 examples: 39 examples:
40 - | 40 - |
41 sysclock: sysclock@fd020004 { 41 sysclock: sysclock@fd020004 {
42 compatible = "fixed-mmio-clock"; 42 compatible = "fixed-mmio-clock";
43 #clock-cells = <0>; 43 #clock-cells = <0>;
44 reg = <0xfd020004 0x4>; 44 reg = <0xfd020004 0x4>;
45 clock-output-names = "sysclk"; 45 clock-output-names = "sysclk";
46 }; 46 };
47 ... 47 ...
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