1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/imx28 4 $id: http://devicetree.org/schemas/clock/imx28-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX28 Clock Controller 7 title: Freescale i.MX28 Clock Controller
8 8
9 maintainers: 9 maintainers:
10 - Shawn Guo <shawnguo@kernel.org> 10 - Shawn Guo <shawnguo@kernel.org>
11 11
12 description: | 12 description: |
13 The clock consumer should specify the desire 13 The clock consumer should specify the desired clock by having the clock
14 ID in its "clocks" phandle cell. The followi 14 ID in its "clocks" phandle cell. The following is a full list of i.MX28
15 clocks and IDs. 15 clocks and IDs.
16 16
17 Clock ID 17 Clock ID
18 ------------------ 18 ------------------
19 ref_xtal 0 19 ref_xtal 0
20 pll0 1 20 pll0 1
21 pll1 2 21 pll1 2
22 pll2 3 22 pll2 3
23 ref_cpu 4 23 ref_cpu 4
24 ref_emi 5 24 ref_emi 5
25 ref_io0 6 25 ref_io0 6
26 ref_io1 7 26 ref_io1 7
27 ref_pix 8 27 ref_pix 8
28 ref_hsadc 9 28 ref_hsadc 9
29 ref_gpmi 10 29 ref_gpmi 10
30 saif0_sel 11 30 saif0_sel 11
31 saif1_sel 12 31 saif1_sel 12
32 gpmi_sel 13 32 gpmi_sel 13
33 ssp0_sel 14 33 ssp0_sel 14
34 ssp1_sel 15 34 ssp1_sel 15
35 ssp2_sel 16 35 ssp2_sel 16
36 ssp3_sel 17 36 ssp3_sel 17
37 emi_sel 18 37 emi_sel 18
38 etm_sel 19 38 etm_sel 19
39 lcdif_sel 20 39 lcdif_sel 20
40 cpu 21 40 cpu 21
41 ptp_sel 22 41 ptp_sel 22
42 cpu_pll 23 42 cpu_pll 23
43 cpu_xtal 24 43 cpu_xtal 24
44 hbus 25 44 hbus 25
45 xbus 26 45 xbus 26
46 ssp0_div 27 46 ssp0_div 27
47 ssp1_div 28 47 ssp1_div 28
48 ssp2_div 29 48 ssp2_div 29
49 ssp3_div 30 49 ssp3_div 30
50 gpmi_div 31 50 gpmi_div 31
51 emi_pll 32 51 emi_pll 32
52 emi_xtal 33 52 emi_xtal 33
53 lcdif_div 34 53 lcdif_div 34
54 etm_div 35 54 etm_div 35
55 ptp 36 55 ptp 36
56 saif0_div 37 56 saif0_div 37
57 saif1_div 38 57 saif1_div 38
58 clk32k_div 39 58 clk32k_div 39
59 rtc 40 59 rtc 40
60 lradc 41 60 lradc 41
61 spdif_div 42 61 spdif_div 42
62 clk32k 43 62 clk32k 43
63 pwm 44 63 pwm 44
64 uart 45 64 uart 45
65 ssp0 46 65 ssp0 46
66 ssp1 47 66 ssp1 47
67 ssp2 48 67 ssp2 48
68 ssp3 49 68 ssp3 49
69 gpmi 50 69 gpmi 50
70 spdif 51 70 spdif 51
71 emi 52 71 emi 52
72 saif0 53 72 saif0 53
73 saif1 54 73 saif1 54
74 lcdif 55 74 lcdif 55
75 etm 56 75 etm 56
76 fec 57 76 fec 57
77 can0 58 77 can0 58
78 can1 59 78 can1 59
79 usb0 60 79 usb0 60
80 usb1 61 80 usb1 61
81 usb0_phy 62 81 usb0_phy 62
82 usb1_phy 63 82 usb1_phy 63
83 enet_out 64 83 enet_out 64
84 84
85 properties: 85 properties:
86 compatible: 86 compatible:
87 const: fsl,imx28-clkctrl 87 const: fsl,imx28-clkctrl
88 88
89 reg: 89 reg:
90 maxItems: 1 90 maxItems: 1
91 91
92 '#clock-cells': 92 '#clock-cells':
93 const: 1 93 const: 1
94 94
95 required: 95 required:
96 - compatible 96 - compatible
97 - reg 97 - reg
98 - '#clock-cells' 98 - '#clock-cells'
99 99
100 additionalProperties: false 100 additionalProperties: false
101 101
102 examples: 102 examples:
103 - | 103 - |
104 clock-controller@80040000 { 104 clock-controller@80040000 {
105 compatible = "fsl,imx28-clkctrl"; 105 compatible = "fsl,imx28-clkctrl";
106 reg = <0x80040000 0x2000>; 106 reg = <0x80040000 0x2000>;
107 #clock-cells = <1>; 107 #clock-cells = <1>;
108 }; 108 };
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