1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/imx35 4 $id: http://devicetree.org/schemas/clock/imx35-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX35 Clock Controller !! 7 title: Clock bindings for Freescale i.MX35
8 8
9 maintainers: 9 maintainers:
10 - Steffen Trumtrar <s.trumtrar@pengutronix.de 10 - Steffen Trumtrar <s.trumtrar@pengutronix.de>
11 11
12 description: | 12 description: |
13 The clock consumer should specify the desire 13 The clock consumer should specify the desired clock by having the clock
14 ID in its "clocks" phandle cell. The followi 14 ID in its "clocks" phandle cell. The following is a full list of i.MX35
15 clocks and IDs. 15 clocks and IDs.
16 16
17 Clock ID 17 Clock ID
18 --------------------------- 18 ---------------------------
19 ckih 0 19 ckih 0
20 mpll 1 20 mpll 1
21 ppll 2 21 ppll 2
22 mpll_075 3 22 mpll_075 3
23 arm 4 23 arm 4
24 hsp 5 24 hsp 5
25 hsp_div 6 25 hsp_div 6
26 hsp_sel 7 26 hsp_sel 7
27 ahb 8 27 ahb 8
28 ipg 9 28 ipg 9
29 arm_per_div 10 29 arm_per_div 10
30 ahb_per_div 11 30 ahb_per_div 11
31 ipg_per 12 31 ipg_per 12
32 uart_sel 13 32 uart_sel 13
33 uart_div 14 33 uart_div 14
34 esdhc_sel 15 34 esdhc_sel 15
35 esdhc1_div 16 35 esdhc1_div 16
36 esdhc2_div 17 36 esdhc2_div 17
37 esdhc3_div 18 37 esdhc3_div 18
38 spdif_sel 19 38 spdif_sel 19
39 spdif_div_pre 20 39 spdif_div_pre 20
40 spdif_div_post 21 40 spdif_div_post 21
41 ssi_sel 22 41 ssi_sel 22
42 ssi1_div_pre 23 42 ssi1_div_pre 23
43 ssi1_div_post 24 43 ssi1_div_post 24
44 ssi2_div_pre 25 44 ssi2_div_pre 25
45 ssi2_div_post 26 45 ssi2_div_post 26
46 usb_sel 27 46 usb_sel 27
47 usb_div 28 47 usb_div 28
48 nfc_div 29 48 nfc_div 29
49 asrc_gate 30 49 asrc_gate 30
50 pata_gate 31 50 pata_gate 31
51 audmux_gate 32 51 audmux_gate 32
52 can1_gate 33 52 can1_gate 33
53 can2_gate 34 53 can2_gate 34
54 cspi1_gate 35 54 cspi1_gate 35
55 cspi2_gate 36 55 cspi2_gate 36
56 ect_gate 37 56 ect_gate 37
57 edio_gate 38 57 edio_gate 38
58 emi_gate 39 58 emi_gate 39
59 epit1_gate 40 59 epit1_gate 40
60 epit2_gate 41 60 epit2_gate 41
61 esai_gate 42 61 esai_gate 42
62 esdhc1_gate 43 62 esdhc1_gate 43
63 esdhc2_gate 44 63 esdhc2_gate 44
64 esdhc3_gate 45 64 esdhc3_gate 45
65 fec_gate 46 65 fec_gate 46
66 gpio1_gate 47 66 gpio1_gate 47
67 gpio2_gate 48 67 gpio2_gate 48
68 gpio3_gate 49 68 gpio3_gate 49
69 gpt_gate 50 69 gpt_gate 50
70 i2c1_gate 51 70 i2c1_gate 51
71 i2c2_gate 52 71 i2c2_gate 52
72 i2c3_gate 53 72 i2c3_gate 53
73 iomuxc_gate 54 73 iomuxc_gate 54
74 ipu_gate 55 74 ipu_gate 55
75 kpp_gate 56 75 kpp_gate 56
76 mlb_gate 57 76 mlb_gate 57
77 mshc_gate 58 77 mshc_gate 58
78 owire_gate 59 78 owire_gate 59
79 pwm_gate 60 79 pwm_gate 60
80 rngc_gate 61 80 rngc_gate 61
81 rtc_gate 62 81 rtc_gate 62
82 rtic_gate 63 82 rtic_gate 63
83 scc_gate 64 83 scc_gate 64
84 sdma_gate 65 84 sdma_gate 65
85 spba_gate 66 85 spba_gate 66
86 spdif_gate 67 86 spdif_gate 67
87 ssi1_gate 68 87 ssi1_gate 68
88 ssi2_gate 69 88 ssi2_gate 69
89 uart1_gate 70 89 uart1_gate 70
90 uart2_gate 71 90 uart2_gate 71
91 uart3_gate 72 91 uart3_gate 72
92 usbotg_gate 73 92 usbotg_gate 73
93 wdog_gate 74 93 wdog_gate 74
94 max_gate 75 94 max_gate 75
95 admux_gate 76 95 admux_gate 76
96 csi_gate 77 96 csi_gate 77
97 csi_div 78 97 csi_div 78
98 csi_sel 79 98 csi_sel 79
99 iim_gate 80 99 iim_gate 80
100 gpu2d_gate 81 100 gpu2d_gate 81
101 ckli_gate 82 101 ckli_gate 82
102 102
103 properties: 103 properties:
104 compatible: 104 compatible:
105 const: fsl,imx35-ccm 105 const: fsl,imx35-ccm
106 106
107 reg: 107 reg:
108 maxItems: 1 108 maxItems: 1
109 109
110 interrupts: 110 interrupts:
111 maxItems: 1 111 maxItems: 1
112 112
113 '#clock-cells': 113 '#clock-cells':
114 const: 1 114 const: 1
115 115
116 required: 116 required:
117 - compatible 117 - compatible
118 - reg 118 - reg
119 - interrupts 119 - interrupts
120 - '#clock-cells' 120 - '#clock-cells'
121 121
122 additionalProperties: false 122 additionalProperties: false
123 123
124 examples: 124 examples:
125 - | 125 - |
126 clock-controller@53f80000 { 126 clock-controller@53f80000 {
127 compatible = "fsl,imx35-ccm"; 127 compatible = "fsl,imx35-ccm";
128 reg = <0x53f80000 0x4000>; 128 reg = <0x53f80000 0x4000>;
129 interrupts = <31>; 129 interrupts = <31>;
130 #clock-cells = <1>; 130 #clock-cells = <1>;
>> 131 };
>> 132
>> 133 esdhc@53fb4000 {
>> 134 compatible = "fsl,imx35-esdhc";
>> 135 reg = <0x53fb4000 0x4000>;
>> 136 interrupts = <7>;
>> 137 clocks = <&clks 9>, <&clks 8>, <&clks 43>;
>> 138 clock-names = "ipg", "ahb", "per";
131 }; 139 };
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