1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/imx7u 4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX7ULP Peripheral Clock Con 7 title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller
8 8
9 maintainers: 9 maintainers:
10 - A.s. Dong <aisheng.dong@nxp.com> 10 - A.s. Dong <aisheng.dong@nxp.com>
11 11
12 description: | 12 description: |
13 i.MX7ULP Clock functions are under joint con 13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral C 14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
15 modules, and Core Mode Controller (CMC)1 blo 15 modules, and Core Mode Controller (CMC)1 blocks
16 16
17 The clocking scheme provides clear separatio 17 The clocking scheme provides clear separation between M4 domain
18 and A7 domain. Except for a few clock source 18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock 19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
20 and and the Fast IRC clock (FIRCLK), clock s 20 and and the Fast IRC clock (FIRCLK), clock sources and clock
21 management are separated and contained withi 21 management are separated and contained within each domain.
22 22
23 M4 clock management consists of SCG0, PCC0, 23 M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
24 A7 clock management consists of SCG1, PCC2, 24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
25 25
26 Note: this binding doc is only for A7 clock 26 Note: this binding doc is only for A7 clock domain.
27 27
28 The Peripheral Clock Control (PCC) is respon 28 The Peripheral Clock Control (PCC) is responsible for clock selection,
29 optional division and clock gating mode for 29 optional division and clock gating mode for peripherals in their
30 respected power domain. 30 respected power domain.
31 31
32 The clock consumer should specify the desire 32 The clock consumer should specify the desired clock by having the clock
33 ID in its "clocks" phandle cell. 33 ID in its "clocks" phandle cell.
34 See include/dt-bindings/clock/imx7ulp-clock. 34 See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
35 i.MX7ULP clock IDs of each module. 35 i.MX7ULP clock IDs of each module.
36 36
37 properties: 37 properties:
38 compatible: 38 compatible:
39 enum: 39 enum:
40 - fsl,imx7ulp-pcc2 40 - fsl,imx7ulp-pcc2
41 - fsl,imx7ulp-pcc3 41 - fsl,imx7ulp-pcc3
42 42
43 reg: 43 reg:
44 maxItems: 1 44 maxItems: 1
45 45
46 '#clock-cells': 46 '#clock-cells':
47 const: 1 47 const: 1
48 48
49 clocks: 49 clocks:
50 items: 50 items:
51 - description: nic1 bus clock 51 - description: nic1 bus clock
52 - description: nic1 clock 52 - description: nic1 clock
53 - description: ddr clock 53 - description: ddr clock
54 - description: apll pfd2 54 - description: apll pfd2
55 - description: apll pfd1 55 - description: apll pfd1
56 - description: apll pfd0 56 - description: apll pfd0
57 - description: usb pll 57 - description: usb pll
58 - description: system osc bus clock 58 - description: system osc bus clock
59 - description: fast internal reference c 59 - description: fast internal reference clock bus
60 - description: rtc osc 60 - description: rtc osc
61 - description: system pll bus clock 61 - description: system pll bus clock
62 62
63 clock-names: 63 clock-names:
64 items: 64 items:
65 - const: nic1_bus_clk 65 - const: nic1_bus_clk
66 - const: nic1_clk 66 - const: nic1_clk
67 - const: ddr_clk 67 - const: ddr_clk
68 - const: apll_pfd2 68 - const: apll_pfd2
69 - const: apll_pfd1 69 - const: apll_pfd1
70 - const: apll_pfd0 70 - const: apll_pfd0
71 - const: upll 71 - const: upll
72 - const: sosc_bus_clk 72 - const: sosc_bus_clk
73 - const: firc_bus_clk 73 - const: firc_bus_clk
74 - const: rosc 74 - const: rosc
75 - const: spll_bus_clk 75 - const: spll_bus_clk
76 76
77 required: 77 required:
78 - compatible 78 - compatible
79 - reg 79 - reg
80 - '#clock-cells' 80 - '#clock-cells'
81 - clocks 81 - clocks
82 - clock-names 82 - clock-names
83 83
84 additionalProperties: false 84 additionalProperties: false
85 85
86 examples: 86 examples:
87 - | 87 - |
88 #include <dt-bindings/clock/imx7ulp-clock. 88 #include <dt-bindings/clock/imx7ulp-clock.h>
89 #include <dt-bindings/interrupt-controller 89 #include <dt-bindings/interrupt-controller/arm-gic.h>
90 90
91 clock-controller@403f0000 { 91 clock-controller@403f0000 {
92 compatible = "fsl,imx7ulp-pcc2"; 92 compatible = "fsl,imx7ulp-pcc2";
93 reg = <0x403f0000 0x10000>; 93 reg = <0x403f0000 0x10000>;
94 #clock-cells = <1>; 94 #clock-cells = <1>;
95 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_D 95 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
96 <&scg1 IMX7ULP_CLK_NIC1_DIV>, 96 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
97 <&scg1 IMX7ULP_CLK_DDR_DIV>, 97 <&scg1 IMX7ULP_CLK_DDR_DIV>,
98 <&scg1 IMX7ULP_CLK_APLL_PFD2> 98 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
99 <&scg1 IMX7ULP_CLK_APLL_PFD1> 99 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
100 <&scg1 IMX7ULP_CLK_APLL_PFD0> 100 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
101 <&scg1 IMX7ULP_CLK_UPLL>, 101 <&scg1 IMX7ULP_CLK_UPLL>,
102 <&scg1 IMX7ULP_CLK_SOSC_BUS_C 102 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
103 <&scg1 IMX7ULP_CLK_FIRC_BUS_C 103 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
104 <&scg1 IMX7ULP_CLK_ROSC>, 104 <&scg1 IMX7ULP_CLK_ROSC>,
105 <&scg1 IMX7ULP_CLK_SPLL_BUS_C 105 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
106 clock-names = "nic1_bus_clk", "nic1_c 106 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
107 "apll_pfd2", "apll_pfd1 107 "apll_pfd2", "apll_pfd1", "apll_pfd0",
108 "upll", "sosc_bus_clk", 108 "upll", "sosc_bus_clk", "firc_bus_clk",
109 "rosc", "spll_bus_clk"; 109 "rosc", "spll_bus_clk";
110 }; 110 };
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