1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/imx7u 4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Freescale i.MX7ULP System Clock Generat 7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
8 8
9 maintainers: 9 maintainers:
10 - A.s. Dong <aisheng.dong@nxp.com> 10 - A.s. Dong <aisheng.dong@nxp.com>
11 11
12 description: | 12 description: |
13 i.MX7ULP Clock functions are under joint con 13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral C 14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
15 modules, and Core Mode Controller (CMC)1 blo 15 modules, and Core Mode Controller (CMC)1 blocks
16 16
17 The clocking scheme provides clear separatio 17 The clocking scheme provides clear separation between M4 domain
18 and A7 domain. Except for a few clock source 18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock 19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
20 and and the Fast IRC clock (FIRCLK), clock s 20 and and the Fast IRC clock (FIRCLK), clock sources and clock
21 management are separated and contained withi 21 management are separated and contained within each domain.
22 22
23 M4 clock management consists of SCG0, PCC0, 23 M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
24 A7 clock management consists of SCG1, PCC2, 24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
25 25
26 Note: this binding doc is only for A7 clock 26 Note: this binding doc is only for A7 clock domain.
27 27
28 The System Clock Generation (SCG) is respons 28 The System Clock Generation (SCG) is responsible for clock generation
29 and distribution across this device. Functio 29 and distribution across this device. Functions performed by the SCG
30 include: clock reference selection, generati 30 include: clock reference selection, generation of clock used to derive
31 processor, system, peripheral bus and extern 31 processor, system, peripheral bus and external memory interface clocks,
32 source selection for peripheral clocks and c 32 source selection for peripheral clocks and control of power saving
33 clock gating mode. 33 clock gating mode.
34 34
35 The clock consumer should specify the desire 35 The clock consumer should specify the desired clock by having the clock
36 ID in its "clocks" phandle cell. 36 ID in its "clocks" phandle cell.
37 See include/dt-bindings/clock/imx7ulp-clock. 37 See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
38 i.MX7ULP clock IDs of each module. 38 i.MX7ULP clock IDs of each module.
39 39
40 properties: 40 properties:
41 compatible: 41 compatible:
42 const: fsl,imx7ulp-scg1 42 const: fsl,imx7ulp-scg1
43 43
44 reg: 44 reg:
45 maxItems: 1 45 maxItems: 1
46 46
47 '#clock-cells': 47 '#clock-cells':
48 const: 1 48 const: 1
49 49
50 clocks: 50 clocks:
51 items: 51 items:
52 - description: rtc osc 52 - description: rtc osc
53 - description: system osc 53 - description: system osc
54 - description: slow internal reference c 54 - description: slow internal reference clock
55 - description: fast internal reference c 55 - description: fast internal reference clock
56 - description: usb PLL 56 - description: usb PLL
57 57
58 clock-names: 58 clock-names:
59 items: 59 items:
60 - const: rosc 60 - const: rosc
61 - const: sosc 61 - const: sosc
62 - const: sirc 62 - const: sirc
63 - const: firc 63 - const: firc
64 - const: upll 64 - const: upll
65 65
66 required: 66 required:
67 - compatible 67 - compatible
68 - reg 68 - reg
69 - '#clock-cells' 69 - '#clock-cells'
70 - clocks 70 - clocks
71 - clock-names 71 - clock-names
72 72
73 additionalProperties: false 73 additionalProperties: false
74 74
75 examples: 75 examples:
76 - | 76 - |
77 #include <dt-bindings/clock/imx7ulp-clock. 77 #include <dt-bindings/clock/imx7ulp-clock.h>
78 #include <dt-bindings/interrupt-controller 78 #include <dt-bindings/interrupt-controller/arm-gic.h>
79 79
80 clock-controller@403e0000 { 80 clock-controller@403e0000 {
81 compatible = "fsl,imx7ulp-scg1"; 81 compatible = "fsl,imx7ulp-scg1";
82 reg = <0x403e0000 0x10000>; 82 reg = <0x403e0000 0x10000>;
83 clocks = <&rosc>, <&sosc>, <&sirc>, 83 clocks = <&rosc>, <&sosc>, <&sirc>,
84 <&firc>, <&upll>; 84 <&firc>, <&upll>;
85 clock-names = "rosc", "sosc", "sirc", 85 clock-names = "rosc", "sosc", "sirc",
86 "firc", "upll"; 86 "firc", "upll";
87 #clock-cells = <1>; 87 #clock-cells = <1>;
88 }; 88 };
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