1 Binding for keystone PLLs. The main PLL IP typ 1 Binding for keystone PLLs. The main PLL IP typically has a multiplier,
2 a divider and a post divider. The additional P 2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
3 and PAPLL are controlled by the memory mapped 3 and PAPLL are controlled by the memory mapped register where as the Main
4 PLL is controlled by a PLL controller register 4 PLL is controlled by a PLL controller registers along with memory mapped
5 registers. 5 registers.
6 6
7 This binding uses the common clock binding[1]. 7 This binding uses the common clock binding[1].
8 8
9 [1] Documentation/devicetree/bindings/clock/cl 9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 10
11 Required properties: 11 Required properties:
12 - #clock-cells : from common clock binding; sh 12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll- 13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle 14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier regist 15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-div 16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are app 17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If 18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
19 for postdiv 19 for postdiv
20 20
21 Example: 21 Example:
22 mainpllclk: mainpllclk@2310110 { 22 mainpllclk: mainpllclk@2310110 {
23 #clock-cells = <0>; 23 #clock-cells = <0>;
24 compatible = "ti,keystone,main 24 compatible = "ti,keystone,main-pll-clock";
25 clocks = <&refclksys>; 25 clocks = <&refclksys>;
26 reg = <0x02620350 4>, <0x02310 26 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 reg-names = "control", "multip 27 reg-names = "control", "multiplier", "post-divider";
28 fixed-postdiv = <2>; 28 fixed-postdiv = <2>;
29 }; 29 };
30 30
31 papllclk: papllclk@2620358 { 31 papllclk: papllclk@2620358 {
32 #clock-cells = <0>; 32 #clock-cells = <0>;
33 compatible = "ti,keystone,pll- 33 compatible = "ti,keystone,pll-clock";
34 clocks = <&refclkpass>; 34 clocks = <&refclkpass>;
35 clock-output-names = "pa-pll-c 35 clock-output-names = "pa-pll-clk";
36 reg = <0x02620358 4>; 36 reg = <0x02620358 4>;
37 reg-names = "control"; 37 reg-names = "control";
38 }; 38 };
39 39
40 Required properties: 40 Required properties:
41 - #clock-cells : from common clock binding; sh 41 - #clock-cells : from common clock binding; shall be set to 0.
42 - compatible : shall be "ti,keystone,pll-mux-c 42 - compatible : shall be "ti,keystone,pll-mux-clock"
43 - clocks : link phandles of parent clocks 43 - clocks : link phandles of parent clocks
44 - reg - pll mux register 44 - reg - pll mux register
45 - bit-shift : number of bits to shift the bit- 45 - bit-shift : number of bits to shift the bit-mask
46 - bit-mask : arbitrary bitmask for programming 46 - bit-mask : arbitrary bitmask for programming the mux
47 47
48 Optional properties: 48 Optional properties:
49 - clock-output-names : From common clock bindi 49 - clock-output-names : From common clock binding.
50 50
51 Example: 51 Example:
52 mainmuxclk: mainmuxclk@2310108 { 52 mainmuxclk: mainmuxclk@2310108 {
53 #clock-cells = <0>; 53 #clock-cells = <0>;
54 compatible = "ti,keystone,pll- 54 compatible = "ti,keystone,pll-mux-clock";
55 clocks = <&mainpllclk>, <&refc 55 clocks = <&mainpllclk>, <&refclkmain>;
56 reg = <0x02310108 4>; 56 reg = <0x02310108 4>;
57 bit-shift = <23>; 57 bit-shift = <23>;
58 bit-mask = <1>; 58 bit-mask = <1>;
59 clock-output-names = "mainmuxc 59 clock-output-names = "mainmuxclk";
60 }; 60 };
61 61
62 Required properties: 62 Required properties:
63 - #clock-cells : from common clock binding; sh 63 - #clock-cells : from common clock binding; shall be set to 0.
64 - compatible : shall be "ti,keystone,pll-divid 64 - compatible : shall be "ti,keystone,pll-divider-clock"
65 - clocks : parent clock phandle 65 - clocks : parent clock phandle
66 - reg - pll mux register 66 - reg - pll mux register
67 - bit-shift : number of bits to shift the bit- 67 - bit-shift : number of bits to shift the bit-mask
68 - bit-mask : arbitrary bitmask for programming 68 - bit-mask : arbitrary bitmask for programming the divider
69 69
70 Optional properties: 70 Optional properties:
71 - clock-output-names : From common clock bindi 71 - clock-output-names : From common clock binding.
72 72
73 Example: 73 Example:
74 gemtraceclk: gemtraceclk@2310120 { 74 gemtraceclk: gemtraceclk@2310120 {
75 #clock-cells = <0>; 75 #clock-cells = <0>;
76 compatible = "ti,keystone,pll- 76 compatible = "ti,keystone,pll-divider-clock";
77 clocks = <&mainmuxclk>; 77 clocks = <&mainmuxclk>;
78 reg = <0x02310120 4>; 78 reg = <0x02310120 4>;
79 bit-shift = <0>; 79 bit-shift = <0>;
80 bit-mask = <8>; 80 bit-mask = <8>;
81 clock-output-names = "gemtrace 81 clock-output-names = "gemtraceclk";
82 }; 82 };
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