1 * NXP LPC1850 Clock Generation Unit (CGU)
2
3 The CGU generates multiple independent clocks
4 peripheral blocks of the LPC18xx. Each indepen
5 a base clock and itself is one of the inputs t
6 Control Units (CCUs) which control the branch
7 individual peripherals.
8
9 The CGU selects the inputs to the clock genera
10 clock sources, controls the clock generation,
11 of the clock generators through the clock sour
12 stages. Each output stage provides an independ
13 corresponds to one of the base clocks for the
14
15 - Above text taken from NXP LPC1850 User Manu
16
17
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/cl
20
21 Required properties:
22 - compatible:
23 Should be "nxp,lpc1850-cgu"
24 - reg:
25 Shall define the base and range of the
26 containing clock control registers
27 - #clock-cells:
28 Shall have value <1>. The permitted c
29 are the base clock numbers defined bel
30 - clocks:
31 Shall contain a list of phandles for t
32 sources to the CGU. The list shall be
33 order: xtal, 32khz, enet_rx_clk, enet_
34 - clock-indices:
35 Shall be an ordered list of numbers de
36 number provided by the CGU.
37 - clock-output-names:
38 Shall be an ordered list of strings de
39 the clocks provided by the CGU.
40
41 Which base clocks that are available on the CG
42 specific LPC part. Base clocks are numbered fr
43
44 Number: Name: Descri
45 0 BASE_SAFE_CLK Base s
46 1 BASE_USB0_CLK Base c
47 2 BASE_PERIPH_CLK Base c
48 SPI, a
49 3 BASE_USB1_CLK Base c
50 4 BASE_CPU_CLK System
51 and AP
52 5 BASE_SPIFI_CLK Base c
53 6 BASE_SPI_CLK Base c
54 7 BASE_PHY_RX_CLK Base c
55 8 BASE_PHY_TX_CLK Base c
56 9 BASE_APB1_CLK Base c
57 10 BASE_APB3_CLK Base c
58 11 BASE_LCD_CLK Base c
59 12 BASE_ADCHS_CLK Base c
60 13 BASE_SDIO_CLK Base c
61 14 BASE_SSP0_CLK Base c
62 15 BASE_SSP1_CLK Base c
63 16 BASE_UART0_CLK Base c
64 17 BASE_UART1_CLK Base c
65 18 BASE_UART2_CLK Base c
66 19 BASE_UART3_CLK Base c
67 20 BASE_OUT_CLK Base c
68 24-21 - Reserv
69 25 BASE_AUDIO_CLK Base c
70 26 BASE_CGU_OUT0_CLK Base c
71 27 BASE_CGU_OUT1_CLK Base c
72
73 BASE_PERIPH_CLK and BASE_SPI_CLK is only avail
74 BASE_ADCHS_CLK is only available on LPC4370.
75
76
77 Example board file:
78
79 / {
80 clocks {
81 xtal: xtal {
82 compatible = "fixed-cl
83 #clock-cells = <0>;
84 clock-frequency = <120
85 };
86
87 xtal32: xtal32 {
88 compatible = "fixed-cl
89 #clock-cells = <0>;
90 clock-frequency = <327
91 };
92
93 enet_rx_clk: enet_rx_clk {
94 compatible = "fixed-cl
95 #clock-cells = <0>;
96 clock-frequency = <0>;
97 clock-output-names = "
98 };
99
100 enet_tx_clk: enet_tx_clk {
101 compatible = "fixed-cl
102 #clock-cells = <0>;
103 clock-frequency = <0>;
104 clock-output-names = "
105 };
106
107 gp_clkin: gp_clkin {
108 compatible = "fixed-cl
109 #clock-cells = <0>;
110 clock-frequency = <0>;
111 clock-output-names = "
112 };
113 };
114
115 soc {
116 cgu: clock-controller@40050000
117 compatible = "nxp,lpc1
118 reg = <0x40050000 0x10
119 #clock-cells = <1>;
120 clocks = <&xtal>, <&cr
121 };
122
123 /* A CGU and CCU clock consume
124 lcdc: lcdc@40008000 {
125 ...
126 clocks = <&cgu BASE_LC
127 clock-names = "clcdclk
128 ...
129 };
130 };
131 };
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