1 * NXP LPC1850 Clock Generation Unit (CGU) 1 * NXP LPC1850 Clock Generation Unit (CGU)
2 2
3 The CGU generates multiple independent clocks 3 The CGU generates multiple independent clocks for the core and the
4 peripheral blocks of the LPC18xx. Each indepen 4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs t 5 a base clock and itself is one of the inputs to the two Clock
6 Control Units (CCUs) which control the branch 6 Control Units (CCUs) which control the branch clocks to the
7 individual peripherals. 7 individual peripherals.
8 8
9 The CGU selects the inputs to the clock genera 9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, 10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock sour 11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independ 12 stages. Each output stage provides an independent clock source and
13 corresponds to one of the base clocks for the 13 corresponds to one of the base clocks for the LPC18xx.
14 14
15 - Above text taken from NXP LPC1850 User Manu 15 - Above text taken from NXP LPC1850 User Manual.
16 16
17 17
18 This binding uses the common clock binding: 18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/cl 19 Documentation/devicetree/bindings/clock/clock-bindings.txt
20 20
21 Required properties: 21 Required properties:
22 - compatible: 22 - compatible:
23 Should be "nxp,lpc1850-cgu" 23 Should be "nxp,lpc1850-cgu"
24 - reg: 24 - reg:
25 Shall define the base and range of the 25 Shall define the base and range of the address space
26 containing clock control registers 26 containing clock control registers
27 - #clock-cells: 27 - #clock-cells:
28 Shall have value <1>. The permitted c 28 Shall have value <1>. The permitted clock-specifier values
29 are the base clock numbers defined bel 29 are the base clock numbers defined below.
30 - clocks: 30 - clocks:
31 Shall contain a list of phandles for t 31 Shall contain a list of phandles for the external input
32 sources to the CGU. The list shall be 32 sources to the CGU. The list shall be in the following
33 order: xtal, 32khz, enet_rx_clk, enet_ 33 order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin.
34 - clock-indices: 34 - clock-indices:
35 Shall be an ordered list of numbers de 35 Shall be an ordered list of numbers defining the base clock
36 number provided by the CGU. 36 number provided by the CGU.
37 - clock-output-names: 37 - clock-output-names:
38 Shall be an ordered list of strings de 38 Shall be an ordered list of strings defining the names of
39 the clocks provided by the CGU. 39 the clocks provided by the CGU.
40 40
41 Which base clocks that are available on the CG 41 Which base clocks that are available on the CGU depends on the
42 specific LPC part. Base clocks are numbered fr 42 specific LPC part. Base clocks are numbered from 0 to 27.
43 43
44 Number: Name: Descri 44 Number: Name: Description:
45 0 BASE_SAFE_CLK Base s 45 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
46 1 BASE_USB0_CLK Base c 46 1 BASE_USB0_CLK Base clock for USB0
47 2 BASE_PERIPH_CLK Base c 47 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,
48 SPI, a 48 SPI, and SGPIO
49 3 BASE_USB1_CLK Base c 49 3 BASE_USB1_CLK Base clock for USB1
50 4 BASE_CPU_CLK System 50 4 BASE_CPU_CLK System base clock for ARM Cortex-M core
51 and AP 51 and APB peripheral blocks #0 and #2
52 5 BASE_SPIFI_CLK Base c 52 5 BASE_SPIFI_CLK Base clock for SPIFI
53 6 BASE_SPI_CLK Base c 53 6 BASE_SPI_CLK Base clock for SPI
54 7 BASE_PHY_RX_CLK Base c 54 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock
55 8 BASE_PHY_TX_CLK Base c 55 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock
56 9 BASE_APB1_CLK Base c 56 9 BASE_APB1_CLK Base clock for APB peripheral block # 1
57 10 BASE_APB3_CLK Base c 57 10 BASE_APB3_CLK Base clock for APB peripheral block # 3
58 11 BASE_LCD_CLK Base c 58 11 BASE_LCD_CLK Base clock for LCD
59 12 BASE_ADCHS_CLK Base c 59 12 BASE_ADCHS_CLK Base clock for ADCHS
60 13 BASE_SDIO_CLK Base c 60 13 BASE_SDIO_CLK Base clock for SD/MMC
61 14 BASE_SSP0_CLK Base c 61 14 BASE_SSP0_CLK Base clock for SSP0
62 15 BASE_SSP1_CLK Base c 62 15 BASE_SSP1_CLK Base clock for SSP1
63 16 BASE_UART0_CLK Base c 63 16 BASE_UART0_CLK Base clock for UART0
64 17 BASE_UART1_CLK Base c 64 17 BASE_UART1_CLK Base clock for UART1
65 18 BASE_UART2_CLK Base c 65 18 BASE_UART2_CLK Base clock for UART2
66 19 BASE_UART3_CLK Base c 66 19 BASE_UART3_CLK Base clock for UART3
67 20 BASE_OUT_CLK Base c 67 20 BASE_OUT_CLK Base clock for CLKOUT pin
68 24-21 - Reserv 68 24-21 - Reserved
69 25 BASE_AUDIO_CLK Base c 69 25 BASE_AUDIO_CLK Base clock for audio system (I2S)
70 26 BASE_CGU_OUT0_CLK Base c 70 26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output
71 27 BASE_CGU_OUT1_CLK Base c 71 27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output
72 72
73 BASE_PERIPH_CLK and BASE_SPI_CLK is only avail 73 BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.
74 BASE_ADCHS_CLK is only available on LPC4370. 74 BASE_ADCHS_CLK is only available on LPC4370.
75 75
76 76
77 Example board file: 77 Example board file:
78 78
79 / { 79 / {
80 clocks { 80 clocks {
81 xtal: xtal { 81 xtal: xtal {
82 compatible = "fixed-cl 82 compatible = "fixed-clock";
83 #clock-cells = <0>; 83 #clock-cells = <0>;
84 clock-frequency = <120 84 clock-frequency = <12000000>;
85 }; 85 };
86 86
87 xtal32: xtal32 { 87 xtal32: xtal32 {
88 compatible = "fixed-cl 88 compatible = "fixed-clock";
89 #clock-cells = <0>; 89 #clock-cells = <0>;
90 clock-frequency = <327 90 clock-frequency = <32768>;
91 }; 91 };
92 92
93 enet_rx_clk: enet_rx_clk { 93 enet_rx_clk: enet_rx_clk {
94 compatible = "fixed-cl 94 compatible = "fixed-clock";
95 #clock-cells = <0>; 95 #clock-cells = <0>;
96 clock-frequency = <0>; 96 clock-frequency = <0>;
97 clock-output-names = " 97 clock-output-names = "enet_rx_clk";
98 }; 98 };
99 99
100 enet_tx_clk: enet_tx_clk { 100 enet_tx_clk: enet_tx_clk {
101 compatible = "fixed-cl 101 compatible = "fixed-clock";
102 #clock-cells = <0>; 102 #clock-cells = <0>;
103 clock-frequency = <0>; 103 clock-frequency = <0>;
104 clock-output-names = " 104 clock-output-names = "enet_tx_clk";
105 }; 105 };
106 106
107 gp_clkin: gp_clkin { 107 gp_clkin: gp_clkin {
108 compatible = "fixed-cl 108 compatible = "fixed-clock";
109 #clock-cells = <0>; 109 #clock-cells = <0>;
110 clock-frequency = <0>; 110 clock-frequency = <0>;
111 clock-output-names = " 111 clock-output-names = "gp_clkin";
112 }; 112 };
113 }; 113 };
114 114
115 soc { 115 soc {
116 cgu: clock-controller@40050000 116 cgu: clock-controller@40050000 {
117 compatible = "nxp,lpc1 117 compatible = "nxp,lpc1850-cgu";
118 reg = <0x40050000 0x10 118 reg = <0x40050000 0x1000>;
119 #clock-cells = <1>; 119 #clock-cells = <1>;
120 clocks = <&xtal>, <&cr 120 clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
121 }; 121 };
122 122
123 /* A CGU and CCU clock consume 123 /* A CGU and CCU clock consumer */
124 lcdc: lcdc@40008000 { 124 lcdc: lcdc@40008000 {
125 ... 125 ...
126 clocks = <&cgu BASE_LC 126 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
127 clock-names = "clcdclk 127 clock-names = "clcdclk", "apb_pclk";
128 ... 128 ...
129 }; 129 };
130 }; 130 };
131 }; 131 };
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