1 Devicetree bindings for Maxim MAX9485 Programm 1 Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
2 2
3 This device exposes 4 clocks in total: 3 This device exposes 4 clocks in total:
4 4
5 - MAX9485_MCLKOUT: A gated, buffered outp 5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
6 - MAX9485_CLKOUT: A PLL that can be conf 6 - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
7 frequencies 7 frequencies
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for 8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
9 9
10 MAX9485_CLKOUT[1,2] are children of MAX9485_CL 10 MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
11 requests. 11 requests.
12 12
13 Required properties: 13 Required properties:
14 - compatible: "maxim,max9485" 14 - compatible: "maxim,max9485"
15 - clocks: Input clock, must provide 27.0 !! 15 - clocks: Input clock, must provice 27.000 MHz
16 - clock-names: Must be set to "xclk" 16 - clock-names: Must be set to "xclk"
17 - #clock-cells: From common clock binding; sha 17 - #clock-cells: From common clock binding; shall be set to 1
18 18
19 Optional properties: 19 Optional properties:
20 - reset-gpios: GPIO descriptor connec 20 - reset-gpios: GPIO descriptor connected to the #RESET input pin
21 - vdd-supply: A regulator node for V 21 - vdd-supply: A regulator node for Vdd
22 - clock-output-names: Name of output clocks, 22 - clock-output-names: Name of output clocks, as defined in common clock
23 bindings 23 bindings
24 24
25 If not explicitly set, the output names are "m 25 If not explicitly set, the output names are "mclkout", "clkout", "clkout1"
26 and "clkout2". 26 and "clkout2".
27 27
28 Clocks are defined as preprocessor macros in t 28 Clocks are defined as preprocessor macros in the dt-binding header.
29 29
30 Example: 30 Example:
31 31
32 #include <dt-bindings/clock/maxim,max9 32 #include <dt-bindings/clock/maxim,max9485.h>
33 33
34 xo-27mhz: xo-27mhz { 34 xo-27mhz: xo-27mhz {
35 compatible = "fixed-clock"; 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <27000000>; 37 clock-frequency = <27000000>;
38 }; 38 };
39 39
40 &i2c0 { 40 &i2c0 {
41 max9485: audio-clock@63 { 41 max9485: audio-clock@63 {
42 reg = <0x63>; 42 reg = <0x63>;
43 compatible = "maxim,ma 43 compatible = "maxim,max9485";
44 clock-names = "xclk"; 44 clock-names = "xclk";
45 clocks = <&xo-27mhz>; 45 clocks = <&xo-27mhz>;
46 reset-gpios = <&gpio 1 46 reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
47 vdd-supply = <&3v3-reg 47 vdd-supply = <&3v3-reg>;
48 #clock-cells = <1>; 48 #clock-cells = <1>;
49 }; 49 };
50 }; 50 };
51 51
52 // Clock consumer node 52 // Clock consumer node
53 53
54 foo@0 { 54 foo@0 {
55 compatible = "bar,foo"; 55 compatible = "bar,foo";
56 /* ... */ 56 /* ... */
57 clock-names = "foo-input-clk"; 57 clock-names = "foo-input-clk";
58 clocks = <&max9485 MAX9485_CLK 58 clocks = <&max9485 MAX9485_CLKOUT1>;
59 }; 59 };
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