1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/media 4 $id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MediaTek Functional Clock Controller fo 7 title: MediaTek Functional Clock Controller for MT6795
8 8
9 maintainers: 9 maintainers:
10 - AngeloGioacchino Del Regno <angelogioacchin 10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Chun-Jie Chen <chun-jie.chen@mediatek.com> 11 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
12 12
13 description: | 13 description: |
14 The clock architecture in MediaTek like belo 14 The clock architecture in MediaTek like below
15 PLLs --> 15 PLLs -->
16 dividers --> 16 dividers -->
17 muxes 17 muxes
18 --> 18 -->
19 clock gate 19 clock gate
20 20
21 The devices provide clock gate control in di 21 The devices provide clock gate control in different IP blocks.
22 22
23 properties: 23 properties:
24 compatible: 24 compatible:
25 enum: 25 enum:
26 - mediatek,mt6795-mfgcfg 26 - mediatek,mt6795-mfgcfg
27 - mediatek,mt6795-vdecsys 27 - mediatek,mt6795-vdecsys
28 - mediatek,mt6795-vencsys 28 - mediatek,mt6795-vencsys
29 29
30 reg: 30 reg:
31 maxItems: 1 31 maxItems: 1
32 32
33 '#clock-cells': 33 '#clock-cells':
34 const: 1 34 const: 1
35 35
36 required: 36 required:
37 - compatible 37 - compatible
38 - reg 38 - reg
39 - '#clock-cells' 39 - '#clock-cells'
40 40
41 additionalProperties: false 41 additionalProperties: false
42 42
43 examples: 43 examples:
44 - | 44 - |
45 soc { 45 soc {
46 #address-cells = <2>; 46 #address-cells = <2>;
47 #size-cells = <2>; 47 #size-cells = <2>;
48 48
49 mfgcfg: clock-controller@13000000 { 49 mfgcfg: clock-controller@13000000 {
50 compatible = "mediatek,mt6795-mfgc 50 compatible = "mediatek,mt6795-mfgcfg";
51 reg = <0 0x13000000 0 0x1000>; 51 reg = <0 0x13000000 0 0x1000>;
52 #clock-cells = <1>; 52 #clock-cells = <1>;
53 }; 53 };
54 54
55 vdecsys: clock-controller@16000000 { 55 vdecsys: clock-controller@16000000 {
56 compatible = "mediatek,mt6795-vdec 56 compatible = "mediatek,mt6795-vdecsys";
57 reg = <0 0x16000000 0 0x1000>; 57 reg = <0 0x16000000 0 0x1000>;
58 #clock-cells = <1>; 58 #clock-cells = <1>;
59 }; 59 };
60 60
61 vencsys: clock-controller@18000000 { 61 vencsys: clock-controller@18000000 {
62 compatible = "mediatek,mt6795-venc 62 compatible = "mediatek,mt6795-vencsys";
63 reg = <0 0x18000000 0 0x1000>; 63 reg = <0 0x18000000 0 0x1000>;
64 #clock-cells = <1>; 64 #clock-cells = <1>;
65 }; 65 };
66 }; 66 };
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