1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/media 4 $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MT7621 Clock !! 7 title: MT7621 Clock Device Tree Bindings
8 8
9 maintainers: 9 maintainers:
10 - Sergio Paracuellos <sergio.paracuellos@gmai 10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
11 11
12 description: | 12 description: |
13 The MT7621 has a PLL controller from where t 13 The MT7621 has a PLL controller from where the cpu clock is provided
14 as well as derived clocks for the bus and th 14 as well as derived clocks for the bus and the peripherals. It also
15 can gate SoC device clocks. 15 can gate SoC device clocks.
16 16
17 Each clock is assigned an identifier and cli 17 Each clock is assigned an identifier and client nodes use this identifier
18 to specify the clock which they consume. 18 to specify the clock which they consume.
19 19
20 All these identifiers could be found in: 20 All these identifiers could be found in:
21 [1]: <include/dt-bindings/clock/mt7621-clk.h 21 [1]: <include/dt-bindings/clock/mt7621-clk.h>.
22 22
23 The clocks are provided inside a system cont 23 The clocks are provided inside a system controller node.
24 24
25 This node is also a reset provider for all t <<
26 <<
27 Reset related bits are defined in: <<
28 [2]: <include/dt-bindings/reset/mt7621-reset <<
29 <<
30 properties: 25 properties:
31 compatible: 26 compatible:
32 items: 27 items:
33 - const: mediatek,mt7621-sysc 28 - const: mediatek,mt7621-sysc
34 - const: syscon 29 - const: syscon
35 30
36 reg: 31 reg:
37 maxItems: 1 32 maxItems: 1
38 33
39 "#clock-cells": 34 "#clock-cells":
40 description: 35 description:
41 The first cell indicates the clock numbe 36 The first cell indicates the clock number, see [1] for available
42 clocks. 37 clocks.
43 const: 1 38 const: 1
44 39
45 "#reset-cells": <<
46 description: <<
47 The first cell indicates the reset bit w <<
48 [2] for available resets. <<
49 const: 1 <<
50 <<
51 ralink,memctl: 40 ralink,memctl:
52 $ref: /schemas/types.yaml#/definitions/pha 41 $ref: /schemas/types.yaml#/definitions/phandle
53 description: 42 description:
54 phandle of syscon used to control memory 43 phandle of syscon used to control memory registers
55 44
56 clock-output-names: 45 clock-output-names:
57 maxItems: 8 46 maxItems: 8
58 47
59 required: 48 required:
60 - compatible 49 - compatible
61 - reg 50 - reg
62 - '#clock-cells' 51 - '#clock-cells'
63 - ralink,memctl 52 - ralink,memctl
64 53
65 additionalProperties: false 54 additionalProperties: false
66 55
67 examples: 56 examples:
68 - | 57 - |
69 #include <dt-bindings/clock/mt7621-clk.h> 58 #include <dt-bindings/clock/mt7621-clk.h>
70 59
71 sysc: sysc@0 { 60 sysc: sysc@0 {
72 compatible = "mediatek,mt7621-sysc", "sy 61 compatible = "mediatek,mt7621-sysc", "syscon";
73 reg = <0x0 0x100>; 62 reg = <0x0 0x100>;
74 #clock-cells = <1>; 63 #clock-cells = <1>;
75 #reset-cells = <1>; <<
76 ralink,memctl = <&memc>; 64 ralink,memctl = <&memc>;
77 clock-output-names = "xtal", "cpu", "bus 65 clock-output-names = "xtal", "cpu", "bus",
78 "50m", "125m", "150 66 "50m", "125m", "150m",
79 "250m", "270m"; 67 "250m", "270m";
80 }; 68 };
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