1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/media 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MediaTek Functional Clock Controller fo 7 title: MediaTek Functional Clock Controller for MT8192
8 8
9 maintainers: 9 maintainers:
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com> 10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
11 11
12 description: 12 description:
13 The Mediatek functional clock controller pro 13 The Mediatek functional clock controller provides various clocks on MT8192.
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 items: 17 items:
18 - enum: 18 - enum:
19 - mediatek,mt8192-scp_adsp 19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c 20 - mediatek,mt8192-imp_iic_wrap_c
21 - mediatek,mt8192-imp_iic_wrap_e 21 - mediatek,mt8192-imp_iic_wrap_e
22 - mediatek,mt8192-imp_iic_wrap_s 22 - mediatek,mt8192-imp_iic_wrap_s
23 - mediatek,mt8192-imp_iic_wrap_ws 23 - mediatek,mt8192-imp_iic_wrap_ws
24 - mediatek,mt8192-imp_iic_wrap_w 24 - mediatek,mt8192-imp_iic_wrap_w
25 - mediatek,mt8192-imp_iic_wrap_n 25 - mediatek,mt8192-imp_iic_wrap_n
26 - mediatek,mt8192-msdc_top 26 - mediatek,mt8192-msdc_top
27 - mediatek,mt8192-mfgcfg 27 - mediatek,mt8192-mfgcfg
28 - mediatek,mt8192-imgsys 28 - mediatek,mt8192-imgsys
29 - mediatek,mt8192-imgsys2 29 - mediatek,mt8192-imgsys2
30 - mediatek,mt8192-vdecsys_soc 30 - mediatek,mt8192-vdecsys_soc
31 - mediatek,mt8192-vdecsys 31 - mediatek,mt8192-vdecsys
32 - mediatek,mt8192-vencsys 32 - mediatek,mt8192-vencsys
33 - mediatek,mt8192-camsys 33 - mediatek,mt8192-camsys
34 - mediatek,mt8192-camsys_rawa 34 - mediatek,mt8192-camsys_rawa
35 - mediatek,mt8192-camsys_rawb 35 - mediatek,mt8192-camsys_rawb
36 - mediatek,mt8192-camsys_rawc 36 - mediatek,mt8192-camsys_rawc
37 - mediatek,mt8192-ipesys 37 - mediatek,mt8192-ipesys
38 - mediatek,mt8192-mdpsys 38 - mediatek,mt8192-mdpsys
39 39
40 reg: 40 reg:
41 maxItems: 1 41 maxItems: 1
42 42
43 '#clock-cells': 43 '#clock-cells':
44 const: 1 44 const: 1
45 45
46 required: 46 required:
47 - compatible 47 - compatible
48 - reg 48 - reg
49 49
50 additionalProperties: false 50 additionalProperties: false
51 51
52 examples: 52 examples:
53 - | 53 - |
54 scp_adsp: clock-controller@10720000 { 54 scp_adsp: clock-controller@10720000 {
55 compatible = "mediatek,mt8192-scp_adsp 55 compatible = "mediatek,mt8192-scp_adsp";
56 reg = <0x10720000 0x1000>; 56 reg = <0x10720000 0x1000>;
57 #clock-cells = <1>; 57 #clock-cells = <1>;
58 }; 58 };
59 59
60 - | 60 - |
61 imp_iic_wrap_c: clock-controller@11007000 61 imp_iic_wrap_c: clock-controller@11007000 {
62 compatible = "mediatek,mt8192-imp_iic_ 62 compatible = "mediatek,mt8192-imp_iic_wrap_c";
63 reg = <0x11007000 0x1000>; 63 reg = <0x11007000 0x1000>;
64 #clock-cells = <1>; 64 #clock-cells = <1>;
65 }; 65 };
66 66
67 - | 67 - |
68 imp_iic_wrap_e: clock-controller@11cb1000 68 imp_iic_wrap_e: clock-controller@11cb1000 {
69 compatible = "mediatek,mt8192-imp_iic_ 69 compatible = "mediatek,mt8192-imp_iic_wrap_e";
70 reg = <0x11cb1000 0x1000>; 70 reg = <0x11cb1000 0x1000>;
71 #clock-cells = <1>; 71 #clock-cells = <1>;
72 }; 72 };
73 73
74 - | 74 - |
75 imp_iic_wrap_s: clock-controller@11d03000 75 imp_iic_wrap_s: clock-controller@11d03000 {
76 compatible = "mediatek,mt8192-imp_iic_ 76 compatible = "mediatek,mt8192-imp_iic_wrap_s";
77 reg = <0x11d03000 0x1000>; 77 reg = <0x11d03000 0x1000>;
78 #clock-cells = <1>; 78 #clock-cells = <1>;
79 }; 79 };
80 80
81 - | 81 - |
82 imp_iic_wrap_ws: clock-controller@11d23000 82 imp_iic_wrap_ws: clock-controller@11d23000 {
83 compatible = "mediatek,mt8192-imp_iic_ 83 compatible = "mediatek,mt8192-imp_iic_wrap_ws";
84 reg = <0x11d23000 0x1000>; 84 reg = <0x11d23000 0x1000>;
85 #clock-cells = <1>; 85 #clock-cells = <1>;
86 }; 86 };
87 87
88 - | 88 - |
89 imp_iic_wrap_w: clock-controller@11e01000 89 imp_iic_wrap_w: clock-controller@11e01000 {
90 compatible = "mediatek,mt8192-imp_iic_ 90 compatible = "mediatek,mt8192-imp_iic_wrap_w";
91 reg = <0x11e01000 0x1000>; 91 reg = <0x11e01000 0x1000>;
92 #clock-cells = <1>; 92 #clock-cells = <1>;
93 }; 93 };
94 94
95 - | 95 - |
96 imp_iic_wrap_n: clock-controller@11f02000 96 imp_iic_wrap_n: clock-controller@11f02000 {
97 compatible = "mediatek,mt8192-imp_iic_ 97 compatible = "mediatek,mt8192-imp_iic_wrap_n";
98 reg = <0x11f02000 0x1000>; 98 reg = <0x11f02000 0x1000>;
99 #clock-cells = <1>; 99 #clock-cells = <1>;
100 }; 100 };
101 101
102 - | 102 - |
103 msdc_top: clock-controller@11f10000 { 103 msdc_top: clock-controller@11f10000 {
104 compatible = "mediatek,mt8192-msdc_top 104 compatible = "mediatek,mt8192-msdc_top";
105 reg = <0x11f10000 0x1000>; 105 reg = <0x11f10000 0x1000>;
106 #clock-cells = <1>; 106 #clock-cells = <1>;
107 }; 107 };
108 108
109 - | 109 - |
110 mfgcfg: clock-controller@13fbf000 { 110 mfgcfg: clock-controller@13fbf000 {
111 compatible = "mediatek,mt8192-mfgcfg"; 111 compatible = "mediatek,mt8192-mfgcfg";
112 reg = <0x13fbf000 0x1000>; 112 reg = <0x13fbf000 0x1000>;
113 #clock-cells = <1>; 113 #clock-cells = <1>;
114 }; 114 };
115 115
116 - | 116 - |
117 imgsys: clock-controller@15020000 { 117 imgsys: clock-controller@15020000 {
118 compatible = "mediatek,mt8192-imgsys"; 118 compatible = "mediatek,mt8192-imgsys";
119 reg = <0x15020000 0x1000>; 119 reg = <0x15020000 0x1000>;
120 #clock-cells = <1>; 120 #clock-cells = <1>;
121 }; 121 };
122 122
123 - | 123 - |
124 imgsys2: clock-controller@15820000 { 124 imgsys2: clock-controller@15820000 {
125 compatible = "mediatek,mt8192-imgsys2" 125 compatible = "mediatek,mt8192-imgsys2";
126 reg = <0x15820000 0x1000>; 126 reg = <0x15820000 0x1000>;
127 #clock-cells = <1>; 127 #clock-cells = <1>;
128 }; 128 };
129 129
130 - | 130 - |
131 vdecsys_soc: clock-controller@1600f000 { 131 vdecsys_soc: clock-controller@1600f000 {
132 compatible = "mediatek,mt8192-vdecsys_ 132 compatible = "mediatek,mt8192-vdecsys_soc";
133 reg = <0x1600f000 0x1000>; 133 reg = <0x1600f000 0x1000>;
134 #clock-cells = <1>; 134 #clock-cells = <1>;
135 }; 135 };
136 136
137 - | 137 - |
138 vdecsys: clock-controller@1602f000 { 138 vdecsys: clock-controller@1602f000 {
139 compatible = "mediatek,mt8192-vdecsys" 139 compatible = "mediatek,mt8192-vdecsys";
140 reg = <0x1602f000 0x1000>; 140 reg = <0x1602f000 0x1000>;
141 #clock-cells = <1>; 141 #clock-cells = <1>;
142 }; 142 };
143 143
144 - | 144 - |
145 vencsys: clock-controller@17000000 { 145 vencsys: clock-controller@17000000 {
146 compatible = "mediatek,mt8192-vencsys" 146 compatible = "mediatek,mt8192-vencsys";
147 reg = <0x17000000 0x1000>; 147 reg = <0x17000000 0x1000>;
148 #clock-cells = <1>; 148 #clock-cells = <1>;
149 }; 149 };
150 150
151 - | 151 - |
152 camsys: clock-controller@1a000000 { 152 camsys: clock-controller@1a000000 {
153 compatible = "mediatek,mt8192-camsys"; 153 compatible = "mediatek,mt8192-camsys";
154 reg = <0x1a000000 0x1000>; 154 reg = <0x1a000000 0x1000>;
155 #clock-cells = <1>; 155 #clock-cells = <1>;
156 }; 156 };
157 157
158 - | 158 - |
159 camsys_rawa: clock-controller@1a04f000 { 159 camsys_rawa: clock-controller@1a04f000 {
160 compatible = "mediatek,mt8192-camsys_r 160 compatible = "mediatek,mt8192-camsys_rawa";
161 reg = <0x1a04f000 0x1000>; 161 reg = <0x1a04f000 0x1000>;
162 #clock-cells = <1>; 162 #clock-cells = <1>;
163 }; 163 };
164 164
165 - | 165 - |
166 camsys_rawb: clock-controller@1a06f000 { 166 camsys_rawb: clock-controller@1a06f000 {
167 compatible = "mediatek,mt8192-camsys_r 167 compatible = "mediatek,mt8192-camsys_rawb";
168 reg = <0x1a06f000 0x1000>; 168 reg = <0x1a06f000 0x1000>;
169 #clock-cells = <1>; 169 #clock-cells = <1>;
170 }; 170 };
171 171
172 - | 172 - |
173 camsys_rawc: clock-controller@1a08f000 { 173 camsys_rawc: clock-controller@1a08f000 {
174 compatible = "mediatek,mt8192-camsys_r 174 compatible = "mediatek,mt8192-camsys_rawc";
175 reg = <0x1a08f000 0x1000>; 175 reg = <0x1a08f000 0x1000>;
176 #clock-cells = <1>; 176 #clock-cells = <1>;
177 }; 177 };
178 178
179 - | 179 - |
180 ipesys: clock-controller@1b000000 { 180 ipesys: clock-controller@1b000000 {
181 compatible = "mediatek,mt8192-ipesys"; 181 compatible = "mediatek,mt8192-ipesys";
182 reg = <0x1b000000 0x1000>; 182 reg = <0x1b000000 0x1000>;
183 #clock-cells = <1>; 183 #clock-cells = <1>;
184 }; 184 };
185 185
186 - | 186 - |
187 mdpsys: clock-controller@1f000000 { 187 mdpsys: clock-controller@1f000000 {
188 compatible = "mediatek,mt8192-mdpsys"; 188 compatible = "mediatek,mt8192-mdpsys";
189 reg = <0x1f000000 0x1000>; 189 reg = <0x1f000000 0x1000>;
190 #clock-cells = <1>; 190 #clock-cells = <1>;
191 }; 191 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.