1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/micro
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Microchip PolarFire SoC Fabric Clock Co
8
9 maintainers:
10 - Conor Dooley <conor.dooley@microchip.com>
11
12 description: |
13 Microchip PolarFire SoC has 4 Clock Conditio
14 these blocks contains two PLLs and 2 DLLs &
15 the FPGA. For more information see "PolarFir
16 https://onlinedocs.microchip.com/pr/GUID-8F0
17
18 properties:
19 compatible:
20 const: microchip,mpfs-ccc
21
22 reg:
23 items:
24 - description: PLL0's control registers
25 - description: PLL1's control registers
26 - description: DLL0's control registers
27 - description: DLL1's control registers
28
29 clocks:
30 description:
31 The CCC PLL's have two input clocks. It
32 clocks are identical that both are provi
33 minItems: 2
34 items:
35 - description: PLL0's refclk0
36 - description: PLL0's refclk1
37 - description: PLL1's refclk0
38 - description: PLL1's refclk1
39 - description: DLL0's refclk
40 - description: DLL1's refclk
41
42 clock-names:
43 minItems: 2
44 items:
45 - const: pll0_ref0
46 - const: pll0_ref1
47 - const: pll1_ref0
48 - const: pll1_ref1
49 - const: dll0_ref
50 - const: dll1_ref
51
52 '#clock-cells':
53 const: 1
54 description: |
55 The clock consumer should specify the de
56 ID in its "clocks" phandle cell.
57 See include/dt-bindings/clock/microchip,
58 PolarFire clock IDs.
59
60 required:
61 - compatible
62 - reg
63 - clocks
64 - clock-names
65 - '#clock-cells'
66
67 additionalProperties: false
68
69 examples:
70 - |
71 clock-controller@38100000 {
72 compatible = "microchip,mpfs-ccc";
73 reg = <0x38010000 0x1000>, <0x38020000
74 <0x39010000 0x1000>, <0x39020000
75 #clock-cells = <1>;
76 clocks = <&refclk_ccc>, <&refclk_ccc>,
77 <&refclk_ccc>, <&refclk_ccc>
78 clock-names = "pll0_ref0", "pll0_ref1"
79 "dll0_ref", "dll1_ref";
80 };
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