1 Device Tree Clock bindings for cpu clock of Ma 1 Device Tree Clock bindings for cpu clock of Marvell EBU platforms
2 2
3 Required properties: 3 Required properties:
4 - compatible : shall be one of the following: 4 - compatible : shall be one of the following:
5 "marvell,armada-xp-cpu-clock" - cpu cl 5 "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
6 "marvell,mv98dx3236-cpu-clock" - cpu c 6 "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
7 - reg : Address and length of the clock comple 7 - reg : Address and length of the clock complex register set, followed
8 by address and length of the PMU DFS r 8 by address and length of the PMU DFS registers
9 - #clock-cells : should be set to 1. 9 - #clock-cells : should be set to 1.
10 - clocks : shall be the input parent clock pha 10 - clocks : shall be the input parent clock phandle for the clock.
11 11
12 cpuclk: clock-complex@d0018700 { 12 cpuclk: clock-complex@d0018700 {
13 #clock-cells = <1>; 13 #clock-cells = <1>;
14 compatible = "marvell,armada-xp-cpu-cl 14 compatible = "marvell,armada-xp-cpu-clock";
15 reg = <0xd0018700 0xA0>, <0x1c054 0x10 15 reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
16 clocks = <&coreclk 1>; 16 clocks = <&coreclk 1>;
17 } 17 }
18 18
19 cpu@0 { 19 cpu@0 {
20 compatible = "marvell,sheeva-v7"; 20 compatible = "marvell,sheeva-v7";
21 reg = <0>; 21 reg = <0>;
22 clocks = <&cpuclk 0>; 22 clocks = <&cpuclk 0>;
23 }; 23 };
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