1 Imagination Technologies Pistachio SoC clock c
2 ==============================================
3
4 Pistachio has four clock controllers (core clo
5 general control, and top general control) whic
6 from the device-tree.
7
8 External clocks:
9 ----------------
10
11 There are three external inputs to the clock c
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference cl
15 - "enet_clk_in": Alternate ethernet PHY clock
16
17 Core clock controller:
18 ----------------------
19
20 The core clock controller generates clocks for
21 co-processor), audio, and several peripherals.
22
23 Required properties:
24 - compatible: Must be "img,pistachio-clk".
25 - reg: Must contain the base address and lengt
26 - #clock-cells: Must be 1. The single cell is
27 See dt-bindings/clock/pistachio-clk.h for th
28 - clocks: Must contain an entry for each clock
29 - clock-names: Must include "xtal" (see "Exter
30 "audio_clk_in_gate", "enet_clk_in_gate" whic
31 top-level general control.
32
33 Example:
34 clk_core: clock-controller@18144000 {
35 compatible = "img,pistachio-cl
36 reg = <0x18144000 0x800>;
37 clocks = <&xtal>, <&cr_top EXT
38 <&cr_top EXT_CLK_ENET
39 clock-names = "xtal", "audio_c
40
41 #clock-cells = <1>;
42 };
43
44 Peripheral clock controller:
45 ----------------------------
46
47 The peripheral clock controller generates cloc
48 peripherals. The peripheral system clock ("pe
49 clock controller is the input clock to the per
50
51 Required properties:
52 - compatible: Must be "img,pistachio-periph-cl
53 - reg: Must contain the base address and lengt
54 controller.
55 - #clock-cells: Must be 1. The single cell is
56 See dt-bindings/clock/pistachio-clk.h for th
57 - clocks: Must contain an entry for each clock
58 - clock-names: Must include "periph_sys", the
59 by the core clock controller.
60
61 Example:
62 clk_periph: clock-controller@18144800
63 compatible = "img,pistachio-cl
64 reg = <0x18144800 0x800>;
65 clocks = <&clk_core CLK_PERIPH
66 clock-names = "periph_sys";
67
68 #clock-cells = <1>;
69 };
70
71 Peripheral general control:
72 ---------------------------
73
74 The peripheral general control block generates
75 resets for various peripherals. It also conta
76 control registers. The system clock ("sys") g
77 controller is the input clock to the system cl
78
79 Required properties:
80 - compatible: Must include "img,pistachio-peri
81 - reg: Must contain the base address and lengt
82 control registers.
83 - #clock-cells: Must be 1. The single cell is
84 See dt-bindings/clock/pistachio-clk.h for th
85 - clocks: Must contain an entry for each clock
86 - clock-names: Must include "sys", the system
87 clock controller.
88
89 Example:
90 cr_periph: syscon@18144800 {
91 compatible = "img,pistachio-cr
92 reg = <0x18148000 0x1000>;
93 clocks = <&clock_periph PERIPH
94 clock-names = "sys";
95
96 #clock-cells = <1>;
97 };
98
99 Top-level general control:
100 --------------------------
101
102 The top-level general control block contains m
103 gates for the external clocks "audio_clk_in" a
104
105 Required properties:
106 - compatible: Must include "img,pistachio-cr-t
107 - reg: Must contain the base address and lengt
108 control registers.
109 - clocks: Must contain an entry for each clock
110 - clock-names: Two optional clocks, "audio_clk
111 "External clocks").
112 - #clock-cells: Must be 1. The single cell is
113 See dt-bindings/clock/pistachio-clk.h for th
114
115 Example:
116 cr_top: syscon@18144800 {
117 compatible = "img,pistachio-cr
118 reg = <0x18149000 0x200>;
119 clocks = <&audio_refclk>, <&ex
120 clock-names = "audio_clk_in",
121
122 #clock-cells = <1>;
123 };
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