1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/qcom, 4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Display Clock Controller on SM 7 title: Qualcomm Display Clock Controller on SM6125
8 8
9 maintainers: 9 maintainers:
10 - Martin Botka <martin.botka@somainline.org> 10 - Martin Botka <martin.botka@somainline.org>
11 11
12 description: | 12 description: |
13 Qualcomm display clock control module provid 13 Qualcomm display clock control module provides the clocks and power domains
14 on SM6125. 14 on SM6125.
15 15
16 See also:: include/dt-bindings/clock/qcom,di 16 See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 enum: 20 enum:
21 - qcom,sm6125-dispcc 21 - qcom,sm6125-dispcc
22 22
23 clocks: 23 clocks:
24 items: 24 items:
25 - description: Board XO source 25 - description: Board XO source
26 - description: Byte clock from DSI PHY0 26 - description: Byte clock from DSI PHY0
27 - description: Pixel clock from DSI PHY0 27 - description: Pixel clock from DSI PHY0
28 - description: Pixel clock from DSI PHY1 28 - description: Pixel clock from DSI PHY1
29 - description: Link clock from DP PHY 29 - description: Link clock from DP PHY
30 - description: VCO DIV clock from DP PHY 30 - description: VCO DIV clock from DP PHY
31 - description: AHB config clock from GCC 31 - description: AHB config clock from GCC
32 - description: GPLL0 div source from GCC <<
33 32
34 clock-names: 33 clock-names:
35 items: 34 items:
36 - const: bi_tcxo 35 - const: bi_tcxo
37 - const: dsi0_phy_pll_out_byteclk 36 - const: dsi0_phy_pll_out_byteclk
38 - const: dsi0_phy_pll_out_dsiclk 37 - const: dsi0_phy_pll_out_dsiclk
39 - const: dsi1_phy_pll_out_dsiclk 38 - const: dsi1_phy_pll_out_dsiclk
40 - const: dp_phy_pll_link_clk 39 - const: dp_phy_pll_link_clk
41 - const: dp_phy_pll_vco_div_clk 40 - const: dp_phy_pll_vco_div_clk
42 - const: cfg_ahb_clk 41 - const: cfg_ahb_clk
43 - const: gcc_disp_gpll0_div_clk_src <<
44 42
45 '#clock-cells': 43 '#clock-cells':
46 const: 1 44 const: 1
47 45
48 '#power-domain-cells': 46 '#power-domain-cells':
49 const: 1 47 const: 1
50 48
51 power-domains: <<
52 description: <<
53 A phandle and PM domain specifier for th <<
54 maxItems: 1 <<
55 <<
56 required-opps: <<
57 description: <<
58 A phandle to an OPP node describing the <<
59 maxItems: 1 <<
60 <<
61 reg: 49 reg:
62 maxItems: 1 50 maxItems: 1
63 51
64 required: 52 required:
65 - compatible 53 - compatible
66 - reg 54 - reg
67 - clocks 55 - clocks
68 - clock-names 56 - clock-names
69 - '#clock-cells' 57 - '#clock-cells'
70 - '#power-domain-cells' 58 - '#power-domain-cells'
71 59
72 additionalProperties: false 60 additionalProperties: false
73 61
74 examples: 62 examples:
75 - | 63 - |
76 #include <dt-bindings/clock/qcom,rpmcc.h> 64 #include <dt-bindings/clock/qcom,rpmcc.h>
77 #include <dt-bindings/clock/qcom,gcc-sm612 65 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
78 #include <dt-bindings/power/qcom-rpmpd.h> <<
79 clock-controller@5f00000 { 66 clock-controller@5f00000 {
80 compatible = "qcom,sm6125-dispcc"; 67 compatible = "qcom,sm6125-dispcc";
81 reg = <0x5f00000 0x20000>; 68 reg = <0x5f00000 0x20000>;
82 <<
83 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 69 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
84 <&dsi0_phy 0>, 70 <&dsi0_phy 0>,
85 <&dsi0_phy 1>, 71 <&dsi0_phy 1>,
86 <&dsi1_phy 1>, 72 <&dsi1_phy 1>,
87 <&dp_phy 0>, 73 <&dp_phy 0>,
88 <&dp_phy 1>, 74 <&dp_phy 1>,
89 <&gcc GCC_DISP_AHB_CLK>, !! 75 <&gcc GCC_DISP_AHB_CLK>;
90 <&gcc GCC_DISP_GPLL0_DIV_CLK_SR <<
91 clock-names = "bi_tcxo", 76 clock-names = "bi_tcxo",
92 "dsi0_phy_pll_out_byteclk" 77 "dsi0_phy_pll_out_byteclk",
93 "dsi0_phy_pll_out_dsiclk", 78 "dsi0_phy_pll_out_dsiclk",
94 "dsi1_phy_pll_out_dsiclk", 79 "dsi1_phy_pll_out_dsiclk",
95 "dp_phy_pll_link_clk", 80 "dp_phy_pll_link_clk",
96 "dp_phy_pll_vco_div_clk", 81 "dp_phy_pll_vco_div_clk",
97 "cfg_ahb_clk", !! 82 "cfg_ahb_clk";
98 "gcc_disp_gpll0_div_clk_sr <<
99 <<
100 required-opps = <&rpmhpd_opp_ret>; <<
101 power-domains = <&rpmpd SM6125_VDDCX>; <<
102 <<
103 #clock-cells = <1>; 83 #clock-cells = <1>;
104 #power-domain-cells = <1>; 84 #power-domain-cells = <1>;
105 }; 85 };
106 ... 86 ...
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