1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/clock/qcom, 4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Display Clock Controller on SM 7 title: Qualcomm Display Clock Controller on SM6125
8 8
9 maintainers: 9 maintainers:
10 - Martin Botka <martin.botka@somainline.org> 10 - Martin Botka <martin.botka@somainline.org>
11 11
12 description: | 12 description: |
13 Qualcomm display clock control module provid 13 Qualcomm display clock control module provides the clocks and power domains
14 on SM6125. 14 on SM6125.
15 15
16 See also:: include/dt-bindings/clock/qcom,di 16 See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 enum: 20 enum:
21 - qcom,sm6125-dispcc 21 - qcom,sm6125-dispcc
22 22
23 clocks: 23 clocks:
24 items: 24 items:
25 - description: Board XO source 25 - description: Board XO source
26 - description: Byte clock from DSI PHY0 26 - description: Byte clock from DSI PHY0
27 - description: Pixel clock from DSI PHY0 27 - description: Pixel clock from DSI PHY0
28 - description: Pixel clock from DSI PHY1 28 - description: Pixel clock from DSI PHY1
29 - description: Link clock from DP PHY 29 - description: Link clock from DP PHY
30 - description: VCO DIV clock from DP PHY 30 - description: VCO DIV clock from DP PHY
31 - description: AHB config clock from GCC 31 - description: AHB config clock from GCC
32 - description: GPLL0 div source from GCC 32 - description: GPLL0 div source from GCC
33 33
34 clock-names: 34 clock-names:
35 items: 35 items:
36 - const: bi_tcxo 36 - const: bi_tcxo
37 - const: dsi0_phy_pll_out_byteclk 37 - const: dsi0_phy_pll_out_byteclk
38 - const: dsi0_phy_pll_out_dsiclk 38 - const: dsi0_phy_pll_out_dsiclk
39 - const: dsi1_phy_pll_out_dsiclk 39 - const: dsi1_phy_pll_out_dsiclk
40 - const: dp_phy_pll_link_clk 40 - const: dp_phy_pll_link_clk
41 - const: dp_phy_pll_vco_div_clk 41 - const: dp_phy_pll_vco_div_clk
42 - const: cfg_ahb_clk 42 - const: cfg_ahb_clk
43 - const: gcc_disp_gpll0_div_clk_src 43 - const: gcc_disp_gpll0_div_clk_src
44 44
45 '#clock-cells': 45 '#clock-cells':
46 const: 1 46 const: 1
47 47
48 '#power-domain-cells': 48 '#power-domain-cells':
49 const: 1 49 const: 1
50 50
51 power-domains: 51 power-domains:
52 description: 52 description:
53 A phandle and PM domain specifier for th 53 A phandle and PM domain specifier for the CX power domain.
54 maxItems: 1 54 maxItems: 1
55 55
56 required-opps: 56 required-opps:
57 description: 57 description:
58 A phandle to an OPP node describing the 58 A phandle to an OPP node describing the power domain's performance point.
59 maxItems: 1 59 maxItems: 1
60 60
61 reg: 61 reg:
62 maxItems: 1 62 maxItems: 1
63 63
64 required: 64 required:
65 - compatible 65 - compatible
66 - reg 66 - reg
67 - clocks 67 - clocks
68 - clock-names 68 - clock-names
69 - '#clock-cells' 69 - '#clock-cells'
70 - '#power-domain-cells' 70 - '#power-domain-cells'
71 71
72 additionalProperties: false 72 additionalProperties: false
73 73
74 examples: 74 examples:
75 - | 75 - |
76 #include <dt-bindings/clock/qcom,rpmcc.h> 76 #include <dt-bindings/clock/qcom,rpmcc.h>
77 #include <dt-bindings/clock/qcom,gcc-sm612 77 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
78 #include <dt-bindings/power/qcom-rpmpd.h> 78 #include <dt-bindings/power/qcom-rpmpd.h>
79 clock-controller@5f00000 { 79 clock-controller@5f00000 {
80 compatible = "qcom,sm6125-dispcc"; 80 compatible = "qcom,sm6125-dispcc";
81 reg = <0x5f00000 0x20000>; 81 reg = <0x5f00000 0x20000>;
82 82
83 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 83 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
84 <&dsi0_phy 0>, 84 <&dsi0_phy 0>,
85 <&dsi0_phy 1>, 85 <&dsi0_phy 1>,
86 <&dsi1_phy 1>, 86 <&dsi1_phy 1>,
87 <&dp_phy 0>, 87 <&dp_phy 0>,
88 <&dp_phy 1>, 88 <&dp_phy 1>,
89 <&gcc GCC_DISP_AHB_CLK>, 89 <&gcc GCC_DISP_AHB_CLK>,
90 <&gcc GCC_DISP_GPLL0_DIV_CLK_SR 90 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
91 clock-names = "bi_tcxo", 91 clock-names = "bi_tcxo",
92 "dsi0_phy_pll_out_byteclk" 92 "dsi0_phy_pll_out_byteclk",
93 "dsi0_phy_pll_out_dsiclk", 93 "dsi0_phy_pll_out_dsiclk",
94 "dsi1_phy_pll_out_dsiclk", 94 "dsi1_phy_pll_out_dsiclk",
95 "dp_phy_pll_link_clk", 95 "dp_phy_pll_link_clk",
96 "dp_phy_pll_vco_div_clk", 96 "dp_phy_pll_vco_div_clk",
97 "cfg_ahb_clk", 97 "cfg_ahb_clk",
98 "gcc_disp_gpll0_div_clk_sr 98 "gcc_disp_gpll0_div_clk_src";
99 99
100 required-opps = <&rpmhpd_opp_ret>; 100 required-opps = <&rpmhpd_opp_ret>;
101 power-domains = <&rpmpd SM6125_VDDCX>; 101 power-domains = <&rpmpd SM6125_VDDCX>;
102 102
103 #clock-cells = <1>; 103 #clock-cells = <1>;
104 #power-domain-cells = <1>; 104 #power-domain-cells = <1>;
105 }; 105 };
106 ... 106 ...
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