1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Qualcomm Display Clock & Reset Controll
8
9 maintainers:
10 - Konrad Dybcio <konradybcio@kernel.org>
11
12 description: |
13 Qualcomm display clock control module provid
14 domains on SM6350.
15
16 See also:: include/dt-bindings/clock/qcom,di
17
18 properties:
19 compatible:
20 const: qcom,sm6350-dispcc
21
22 clocks:
23 items:
24 - description: Board XO source
25 - description: GPLL0 source from GCC
26 - description: Byte clock from DSI PHY
27 - description: Pixel clock from DSI PHY
28 - description: Link clock from DP PHY
29 - description: VCO DIV clock from DP PHY
30
31 clock-names:
32 items:
33 - const: bi_tcxo
34 - const: gcc_disp_gpll0_clk
35 - const: dsi0_phy_pll_out_byteclk
36 - const: dsi0_phy_pll_out_dsiclk
37 - const: dp_phy_pll_link_clk
38 - const: dp_phy_pll_vco_div_clk
39
40 required:
41 - compatible
42 - clocks
43 - clock-names
44 - '#power-domain-cells'
45
46 allOf:
47 - $ref: qcom,gcc.yaml#
48
49 unevaluatedProperties: false
50
51 examples:
52 - |
53 #include <dt-bindings/clock/qcom,gcc-sm635
54 #include <dt-bindings/clock/qcom,rpmh.h>
55 clock-controller@af00000 {
56 compatible = "qcom,sm6350-dispcc";
57 reg = <0x0af00000 0x20000>;
58 clocks = <&rpmhcc RPMH_CXO_CLK>,
59 <&gcc GCC_DISP_GPLL0_CLK>,
60 <&dsi_phy 0>,
61 <&dsi_phy 1>,
62 <&dp_phy 0>,
63 <&dp_phy 1>;
64 clock-names = "bi_tcxo",
65 "gcc_disp_gpll0_clk",
66 "dsi0_phy_pll_out_byteclk"
67 "dsi0_phy_pll_out_dsiclk",
68 "dp_phy_pll_link_clk",
69 "dp_phy_pll_vco_div_clk";
70 #clock-cells = <1>;
71 #reset-cells = <1>;
72 #power-domain-cells = <1>;
73 };
74 ...
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